LP62S2048A-I Series
Preliminary
256K X 8 BIT LOW VOLTAGE CMOS SRAM
General Description
Features
nPower supply range: 2.7V to 3.3V
nAccess times: 55/70 ns (max.)
nCurrent:
The LP62S2048A-I is a low operating current 2,097,152-bit
static random access memory organized as 262,144 words
by 8 bits and operates on a low power supply range: 2.7V to
Very low power version: Operating: 55ns: 25mA (max.)
70ns: 20mA (max.)
3.3V. It is built using AMIC's high performance CMOS
process.
Inputs and three-state outputs are TTL compatible and allow
for direct interfacing with common system bus structures.
Two chip enable inputs are provided for POWER-DOWN
and device enable and an output enable input is included for
easy interfacing.
Standby: 10mA (max.)
nFull static operation, no clock or refreshing required
nAll inputs and outputs are directly TTL-compatible
nCommon I/O using three-state output
nOutput enable and two chip enable inputs for easy
application
Data retention is guaranteed at a power supply voltage as
low as 2V.
nData retention voltage: 2V (min.)
nAvailable in 32-pin SOP, TSOP, TSSOP (8X13.4mm)
and 36-pin CSP packages
Product Family
Power Dissipation
Package
Operating
Temperature
VCC
Range
Product Family
Speed
Data Retention
(ICCDR, Typ.)
Standby
Operating
Type
(ISB1, Typ.) (ICC2, Typ.)
32L SOP
32L TSOP
32L TSSOP
36L CSP
LP62S2048A
2.7V~3.3V 55ns / 70ns
3mA
-40°C ~ +85°C
0.5mA
0.5mA
1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested.
2. Data retention current VCC = 2.0V.
PRELIMINARY (June, 2002, Version 0.0)
2
AMIC Technology, Inc.
AMICC [ AMIC TECHNOLOGY ]
