Data Sheet AS1100
Parameter
Symbol Conditions
Input Current DIN, CLK, LOAD I
IH
, I
IL
V
IN
= 0V or VDD
Logic High Input Voltage
V
IH
Logic Low Input Voltage
V
IL
Output High Voltage
V
OH
DOUT, I
SOURCE
= -1mA
Output Low Voltage
V
OL
DOUT, I
SINK
= 1.6mA
Hysteresis Voltage
V
I
DIN, CLK, LOAD
Timing Characteristics
CLK Clock Period
t
CP
CLK Pulse Width High
t
CH
CLK Pulse Width Low
t
CL
CLK Rise to LOAD Rise Hold
t
CSH
Time
DIN Setup Time
t
DS
DIN Hold Time
t
DH
Output Data Propagation Delay
t
DO
C
LOAD
= 50pF
LOAD Rising Edge to Next
t
LDCK
Clock Rising Edge
Minimum LOAD Pulse High
t
CSW
Data-to-Segment Delay
t
DSPD
Min
-1
3.5
VDD - 1
Typ
Max
1
0.8
0.4
1
100
50
50
0
25
0
25
50
50
2.25
Units
µA
V
V
V
V
V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Pin Description
Pin
1
2, 3, 5–8, 10,
11
4, 9
12
13
14–17, 20–23
18
19
24
Name
DIN
Function
Data input. Data is programmed into the 16Bit shift register on the rising CLK edge
8 digit driver lines that sink the current from the common cathode of the display.
DIG 0–DIG 7
In shutdown mode the AS1100 switches the outputs to VDD
GND
both GND pins must be connected
Strobe input. With the rising edge of the LOAD signal the 16 bit of serial data is latched into
LOAD
the register.
Clock input. The interface is capable to support clock frequencies up to 10MHz. The serial
CLK
data is clocked into the internal shift register with the rising edge of the CLK signal. On the
DOUT pin the data is applied with the falling edge of CLK.
SEG A–G,
Seven segment driver lines including the decimal point. When a segment is turned off the
DP
output is connected to GND.
The current into I
SET
determines the peak current through the segments and therefore the
ISET
brightness.
VDD
Positive Supply Voltage (+5V)
Serial data output for cascading drivers. The output is valid after 16.5 clock cycles. The
DOUT
output is never set to high impedance.
Revision 1.32, Oct. 2004
Page 3 of 12
AMSCO [ AUSTRIAMICROSYSTEMS AG ]
