AS5501 / AS5502 Multimode Powerline Modem
Data Sheet
To establish the frequency modulation, the output of the mark/space up/down-counter gets
added to Nmark. There has to be a smooth frequency-change from mark to space and from
space to mark within half the bit-time with 3 intermediate frequencies.
BD1 BD2 Fspace-Fmark
Baud-Rate (CKTX)
600Hz
M/S-UDC BDclk (UDC-CLK)
0
1
0
1
0
0
1
1
600Hz
1200Hz
600Hz
0,1,2,3,4
0,2,4,6,8
0,1,2,3,4
0,2,4,6,8
4800Hz
9600Hz
9600Hz
19200Hz
1200Hz
1200Hz
1200Hz
2400Hz
Example with MRK-REG=8 => Fmark=81.75kHz; BD1,2=0 => dF=BRate=600Hz:
BDR*8
TXD (H=mark)
545
(L=space)
548
N
549
82.35
546 547
82.05
548 547 546 545
82.20
82.20
82.05
81.90
81.75
Fsynth / 16
(kHz)
81.90
81.75
In receive-mode(TxEn=1), a constant number Nmix defined by BD1 gets added to Nmark
instead of the output of the M/S-UDC. This gives a constant frequency which is used as
Mixer-frequency to fold the FSK-signal down to 2.7kHz or 5.4kHz. According to the
mixer-frequency the IF-SC-CLK is defined by the timing-block (see 1.1.3).
BD1 BD2 IFcenter IFbandw
IF-SC-CLK
57.6kHz
Nmix
20
BDclk (UDC-CLK)
4800Hz
0
1
X
X
2700Hz
5400Hz
1200Hz
2400Hz
115.2kHz
40
9600Hz
The second frequency-synthesiser which is a similar structure as described for generating the
FSK-frequencies, is generating the target-frequency for the SCCLK-PLL. To get no
disturbing components, the phase-jitter of the synthesiser has to be reduced by the PLL.
There is a capacitor needed as external low-pass filter, to define the frequency response of the
PLL-loop. To generate the right target-frequency, one half of modulation-depth which is a
factor of 2 or 4 dependent on BD1 has to be added to Nmark. Since the center-frequency is a
very critical parameter, there is a possibility implemented for adjustment by wafersort-trim.
BD1 BD2 Fspace-Fmark (Fcenter-Fmark)/150Hz
Npll
0
1
X
X
600Hz
2
4
MRK_REG + 426 + Itrim + 2
MRK_REG + 426 + Itrim + 4
1200Hz
(Itrim=0 ... 3 defined at wafer-sort)
Rev A, May 2000
Page 10/25
AMSCO [ AMS(艾迈斯) ]
