AS5501 / AS5502 Multimode Powerline Modem
Data Sheet
BIT SEQUENCE
(for A-Mode)
Header (8bit)
Reg. Address (8bit)
Data (8bit)
X X X X X X X 0 X X X X X X A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
R/W bit (0...write, 1...read)
Command bits (available for future use)
B-Mode
Features:
- 2 wire serial bus
- 9 bit data format
- data gets clocked on rising edge and shifted on falling edge
- single and sequential write operation possible
- default polarity of signal SCLK is HIGH
- acknowledge bit (9th bit) output (0 ... data acknowledged)
- D7 is the first bit
- A2 and A1 chip-address bits are internally set to 1
start condition
WRITE OPERATION
nth LSB
acknowledge
output
data
valid
stop condition
SCLK
1st MSB
SD-IN
/SD-OUT
AO/CS
data
valid
1st LSB
data
valid
acknowledge
output
S
t
a
r
t
Header (8bit)
A
C
K
BIT SEQUENCE
Reg. Address (8bit)
A
C
K
Data (8bit)
1 0 1 0 1 1 A0 1 0 X X X X X X A1 A0 0 D7 D6 D5 D4 D3 D2 D1 D0
R/WN bit (0...write, 1...read)
Chip Address bits
A S
C t
K o
0
p
1.1.2 RESET
VREF: A Band Gap Reference block is included for generation of a reference-voltage VREF
with nominal 2.5V needed for an external function (power-fail detection) and as reference for
the power on reset.
POR: A power-on reset function with external adjustable threshold and fixed off-delay
(300ms) defined by the master-clock is implemented. When pin RES-TH is floating the POR-
OFF threshold is nominal 3.75V.There is a hysteresis of typ. 100mV implemented to V-ON.
(In Test-Mode 2 and 3 the Por-delay is reduced to 1.17ms)
Rev A, May 2000
Page 6/25
AMSCO [ AUSTRIAMICROSYSTEMS AG ]
