AS5501 / AS5502 Multimode Powerline Modem
Data Sheet
1.1 SERIF, RESET, TIMING
Default Setting Rom
A0/CS
SD-IN
SCLK
RES-TH
SERIAL INTERFACE
SD-OUT
CONTROL REGISTERS
Control Register Output
POR
BAND GAP REF.
BD1,2, ZCEN, MMV
MCLK
TXEN
ZC
RESN
VREF
CKSYS
TIMING
TXENI
CKTX
IF-SCCLK
SC-CLK
Fmixer
mux
Mclk/2
Test1,2
1.1.1 SERIAL INTERFACE
There is a serial interface implemented for setting the control bits by a CPU.
Three bytes are available with following definitions and default contents (after reset).
Reg.-Name addr
D1
D2
D3
D4
D5
D6
D7
MRK-REG
(def. value)
GLOBAL
(def. value)
TEST
00H
01H
02H
MRK1
1
MRK9
1
TEST1
MRK2
0
BD1
1
TEST2
MRK3
1
BD2
1
ASYN
MRK4
0
RxBw1
1
AgcH
MRK5
0
RxBw2
0
digMix
MRK6
0
ZCEN
1
noTSTin
MRK7
1
MMV
0
TxSyn
D8
MRK8
1
PWD
0
FCdOn
(The default setting of the register "TEST" is always 00h.)
Bit-Name
MRK1-9
BD1,2
RXBW1,2
ZCEN
MMV
PWD
TEST1,2
ASYN
AgcH
digMix
noTSTin
TxSyn
FCdOn
Rev A, May 2000
Function
defines TX Mark Frequency (63.9k-140.55kHz)
defines Baud-Rate and Modulation-Depth
defines RX-BandPassFilter Bandwidth
disable ZeroCrossing TX-Sync
disables transmit Timeout
enables power down mode
enables Test Mode 1-3
disable synchronized receive data RXD
hold AGC counter-state
enables digital mixer; analog mixer enabled by def.
TST-out function only for receiver debugging
enables TXD sampling with CLR/T rising-edge
enables faster CD-ON timing (5/Bdrate)
default val.
453
1, 1
1, 0
1
0
0
0, 0
0
0
0
0
0
0
default function
131.85kHz
2400Hz/1200Hz
4.8kHz @132.45kHz
ZC-disabled
TimeOut enabled
powered up
normal mode
sync. RXD
AGC-loop active
analog mixer
TSTin&out availab.
CLR/T gets synchronised
by TXD-edges
Tcdon=(10/Bdrate)
Page 4/25
AMSCO [ AUSTRIAMICROSYSTEMS AG ]
