Low voltage, Low power, ±1% High detect accuracy CMOS Voltage Detector
Rev. E13-01
VDA Series
DESCRIPTION OF OPERATION
General operation (CMOS Output)
In reference to following the block diagram of CMOS output VDA series ;
V
IN
+
Voltage
Reference
_
P-ch
V
OUT
N-ch
Vss
A.
When the input voltage (V
IN
) is higher than the release voltage (V
REL
), the input voltage (V
IN
) is
provided at the output terminal because N-ch transistor is OFF and the P-ch transistor is ON. And,
the output maintains the same level of input as long as the input voltage remains above the detection
voltage (V
DET
).
B.
When the input voltage (V
IN
) falls below the
detection voltage (V
DET
), the N-ch transistor is
ON and the P-ch transistor is OFF. And, the
output voltage (V
OUT
) is same as ground level
(V
SS
).
C.
When the input voltage (V
IN
) falls below the
minimum operating voltage, the output becomes
unstable, or goes to V
IN
when the output is pulled
up to V
IN
.
D.
When the input voltage (V
IN
) rises above the
minimum voltage, the ground voltage (V
SS
) level
is maintained even though the input voltage (V
IN
)
rises above the detection voltage (V
DET
) as long
as it does not exceed the release voltage (V
REL
)
level.
E.
When the input voltage (V
IN
) rises above the
release voltage (V
REL
), the N-ch transistor
becomes OFF and the P-Ch transistor becomes
ON. And, the output voltage (V
OUT
) is equal to
input voltage (V
IN
). This difference between V
DET
and V
REL
is hysteresis range (V
HYS
).
[ TIMING CHART ]
Input voltage (V
IN
)
Release voltage (V
REL
)
Detection voltage (V
DET
)
Min. operating voltage
Power ground (V
SS
)
Output voltage (V
OUT
)
Release voltage (V
REL
)
Detection voltage (V
DET
)
Hysteresis range (V
HYS
)
Min. operating voltage
Power ground (V
SS
)
A B
C
D E
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