Low voltage, Low power, ±1% High detect accuracy with delay circuit CMOS Voltage Detector
Rev. E13-01
VDD Series
PRODUCTS NUMBERING GUIDE
VDD
Design version
A : TOPR = –40°C ~ +85°C
T : SOT-23
Package form
Output type
C : CMOS output
N : N-channel open drain output
Delay time
S : 10msec~50msec
M : 50msec~200msec
L : 80msec~400msec
Detection accuracy rate
Detection voltage
1 : ±1%
18 ~ 60 : Selectable with a step of 0.1V
in the range of 1.8V ~ 6.0V
e.g.) 18 : 1.8V
30 : 3.0V
PIN CONFIGURATION / MARKING SPECIFICATION (SOT-23)
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Pin Configuration
Vin
3
No.
1
Symbol
Descriptions
V
OUT
SS
IN
Output
2
V
Power ground
Voltage input
A B C D E
3
V
F
F F F
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Marking Specification
2
1
Code
A
Mark
C or N
Contents
Vout
Vss
Output type
Detection voltage
Delay time
Version
(Top view)
BC
D
18~60
S, M or L
A
E
F
Internal rule
Lot number
AnaSem
2
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