欢迎访问ic37.com |
会员登录 免费注册
发布采购

APW7066QAC-TRL 参数 Datasheet PDF下载

APW7066QAC-TRL图片预览
型号: APW7066QAC-TRL
PDF下载: 下载PDF文件 查看货源
内容描述: 双同步降压PWM控制器和一个线性控制器 [Dual Synchronous Buck PWM Controllers and One Linear Controller]
分类和应用: 控制器
文件页数/大小: 34 页 / 971 K
品牌: ANPEC [ ANPEC ELECTRONICS COROPRATION ]
 浏览型号APW7066QAC-TRL的Datasheet PDF文件第5页浏览型号APW7066QAC-TRL的Datasheet PDF文件第6页浏览型号APW7066QAC-TRL的Datasheet PDF文件第7页浏览型号APW7066QAC-TRL的Datasheet PDF文件第8页浏览型号APW7066QAC-TRL的Datasheet PDF文件第10页浏览型号APW7066QAC-TRL的Datasheet PDF文件第11页浏览型号APW7066QAC-TRL的Datasheet PDF文件第12页浏览型号APW7066QAC-TRL的Datasheet PDF文件第13页  
APW7066
Function Pin Descriptions
VCC
Power supply input pin. Connect a nominal 5V power
supply to this pin for the control circuit, or connect a
resistor (nominally 300Ω) to VCC12 for a shunt
regulator function (typical 5.8V). It is recommended
that a decoupling capacitor (1 to 10uF) is connected
to the GND for noise decoupling.
GND
This pin is the signal ground pin. The metal thermal
pad under the package is the IC substrate; connects
the GND pin and metal thermal pad together on the
board, and ties to the good GND plane for electrical
and thermal conduction.
VCC12
Power supply input pin. Connect a nominal 12V power
supply to this pin for the gate driver. It is recommended
that a decoupling capacitor (1 to 10uF) is connected
to the GND for noise decoupling.
PGND
This pin is the power ground pin for the gate driver and
linear driver circuit. It should be tied to the GND.
FB1, FB2, FB3
These pins are the inverting inputs of the error ampli-
fiers of their respective regulators. They are used to
set the output v oltage and the compensation
components.
SS1/EN1, SS2/EN2, SS3/EN3
These pins provide two functions. Connect a capacitor
to the GND for setting the soft-start time. Use an open
drain logic signal to pull the SS/EN pin low to disable
the respective output, leave open to enable the re-
spective output.
COMP1, COMP2
These pins are the outputs of error amplifiers of their
respective regulators. They are used to set the
compensation components.
UGATE1, UGATE2
These pins provide the gate driver for the upper
MOSFETs of VOUT1 and VOUT2.
LGATE1, LGATE2
These pins provide the gate driver for the lower
MOSFETs of VOUT1 and VOUT2.
Copyright
©
ANPEC Electronics Corp.
Rev. A.4 - Jun., 2005
9
www.anpec.com.tw
BOOT1, BOOT2
These pins provide the bootstrap voltage to the gate
driver for driving the upper MOSFETs. It can be
connected to a power voltage directly, but the differ-
ence voltage between the BOOT and VIN must be high
enough to drive the upper MOSFETs.
REFIN
This pin is the reference input voltage of error amplifier
of the VOUT2. It also provides the voltage into a buffer,
which is out on the REFOUT pin.
REFOUT
This pin provides a buffed voltage, which is from REFIN
pin. In Independent mode, it can be used by other
ICs. In DDR mode, it is from the VOUT1, and can be
used as the VTT buffer.
This pin also uses to select the phase shift (see table1).
When this pin pulls to VCC, the buffer is disabled and
the REFOUT is not available for use. It is recommended
that a 0.1uF capacitor is connected to the ground for
stability.
VREF
This pin provides a 3.3V reference voltage, which can
be used by the REFIN pin or other ICs as a voltage
reference. It is recommended that a 1uF capacitor is
connected to ground for stability.
DRIVE3
This pin drives the gate of an external N-channel
MOSFET for linear regulator.
PGOOD
This pin is an open drain device; connect a pull up
resistor to the VCC for PGOOD function.
FS/SYNC
This pin is used to adjust the switching frequency.
Connecting a resistor from FS/SYNC pin to the ground
increases the switching frequency. Conversely, con-
necting a resistor from this pin to the VCC12 reduces
the switching frequency. In addition, this pin also
provides synchronous frequency function. An external
clock can be fed into this pin, and force the switching
frequency to follow the external clock.