APW7067N
Block Diagram
VCC12
Power-On
Reset
Regulator
BOOT
GND
Sense Low Side
UGATE
PHASE
VREF
(0.8V)
10V
O.C.P
Comparator
U.V.P
Comparator
Soft Start
and
Fault Logic
VOCP
0.25V
50%VREF
:
2
Gate Control
LGATE
PGND
Error
Amp 1
PWM
Comparator
U.V.P
Comparator
FBL
10V
:
2
50%VREF
DRIVE
VREF
Error
Amp 2
Oscillator
FS_DIS
Sawtooth
wave
VREF
FB
COMP
Absolute Maximum Ratings
Symbol
VCC12
BOOT
Parameter
Rating
Unit
V
VCC12 to GND
-0.3 to +16
-0.3 to +16
BOOT to PHASE
V
UGATE to PHASE <400ns pulse width
>400ns pulse width
-5 to BOOT+5
-0.3 to BOOT+0.3
UGATE
LGATE
V
V
LGATE to PGND <400ns pulse width
>400ns pulse width
-5 to VCC12+5
-0.3 to VCC12+0.3
PHASE to GND
<400ns pulse width
>400ns pulse width
-5 to +21
-0.3 to 16
PHASE
DRIVE
V
V
V
DRIVE to GND
12
FB, FBL, COMP,
FS_DIS
FB, FBL, COMP, FS_DIS to GND
-0.3 to 7
Copyright ã ANPEC Electronics Corp.
3
www.anpec.com.tw
Rev. A.1 - Jun., 2006
ANPEC [ ANPEC ELECTRONICS COROPRATION ]
