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APW7067NKE-TRL 参数 Datasheet PDF下载

APW7067NKE-TRL图片预览
型号: APW7067NKE-TRL
PDF下载: 下载PDF文件 查看货源
内容描述: 同步降压PWM和线性控制器 [Synchronous Buck PWM and Linear Controller]
分类和应用: 控制器
文件页数/大小: 27 页 / 1591 K
品牌: ANPEC [ ANPEC ELECTRONICS COROPRATION ]
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APW7067N  
Function Pin Descriptions  
VCC12  
- downed immediately.  
Power supply input pin. Connect a nominal 12V power UGATE  
supplyto this pin. The power-on reset function monitors  
This pin is the gate driver for the upper MOSFET of  
the input voltage at this pin. It is recommended that a  
decoupling capacitor (1 to 10mF) be connected toGND  
for noise decoupling.  
PWM output.  
LGATE  
This pin is the gate driver for the lower MOSFET of  
PWM output.  
BOOT  
This pin provides the bootstrap voltage to the upper  
gate driver for driving the N-channel MOSFET. An  
external capacitor from PHASE to BOOT, an internal  
diode, and the power supplyvaltage VCC12, generates  
thebootstrap voltagefor theupper gatediver (UGATE).  
DRIVE  
This pin drives the gate of an external N-channel  
MOSFET for linear regulator. It is also used to set the  
compensation for some specific applications, for  
example, with low values of output capacitance and  
ESR.  
PHASE  
This pin is the return path for the upper gate driver.  
Connect this pin to the upper MOSFET source, and  
connect a capacitor to BOOT for the bootstrap voltage.  
This pin is also used to monitor the voltage drop across  
the lower MOSFET for over-current protection.  
FBL  
This pin is the inverting input of the linear regulator  
error amplifier. It is used to set the output voltage.  
This pin is also monitored for under-voltage protection,  
when theFBL voltage is under 50% of reference voltage  
(0.4V), both outputs will be shutdown immediately.  
GND  
This pin is the signal ground pin. Connect theGNDpin  
to a good ground plane.  
FS_DIS  
This pin be allowed to adjust the switching frequency.  
Connect a resistor from FS_DIS pin to the ground to  
increase the switching frequency. This pin also provides  
shutdown function, use an open drain logic signal to  
pull this pin low to disable both outputs, leave open to  
enable both outputs.  
PGND  
This pin is the power ground pin for the lower gate  
driver. It should be tied to GND pin on the board.  
COMP  
This pin is the output of PWM error amplifier. It is  
used to set the compensation components.  
FB  
ThispinistheinvertinginputofthePWMerror amplifier.  
It is used to set the output voltage and the compensation  
components. This pin is also monitored for under-  
voltage protection, when the FB voltage is under 50%  
of reference voltage (0.4V), both outputs will be shut  
Copyright ã ANPEC Electronics Corp.  
7
www.anpec.com.tw  
Rev. A.1 - Jun., 2006