SRAM
Austin Semiconductor, Inc.
AS5C4009
AC TEST CONDITIONS
Input pulse levels ................................... Vss to 3.0V
Input rise and fall times ....................................... 3ns
Input timing reference levels ............................. 1.5V
Output reference levels ..................................... 1.5V
Output load ......................................... See Figures 1
Q
50
167 ohms
ohms
1.73V
C
C=30pF
= 100pF
Fig. 1 Output Load Equivalent
NOTES
1.
2.
3.
4.
5.
6.
Overshoot: Vcc +3.0V for pulse width < 20ms.
Undershoot: -3V for pulse width < 20ms.
I
CC
is dependent on output loading and cycle rates.
This parameter is guaranteed but not tested.
Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
At any given temperature and voltage condition,
t
HZCE
is less than
t
LZCE
, and
t
HZWE
is less than
t
LZWE
.
WE\ is HIGH for READ cycle.
Device is continuously selected. Chip enables and
output enables are held in their active state.
Address valid prior to, or coincident with, latest
occurring chip enable.
10.
t
RC = Read Cycle Time.
11. Chip enable and write enable can initiate and
terminate a WRITE cycle.
12. Output enable (OE\) is inactive (HIGH).
13. Output enable (OE\) is active (LOW).
14. ASI does not warrant functionality nor reliability of
any product in which the junction temperature
exceeds 150°C. Care should be taken to limit power to
acceptable levels.
15. All voltage referenced to Vss (GND).
7.
8.
9.
DATA RETENTION ELECTRICAL CHARACTERISTICS
DESCRIPTION
V
CC
for Retention Data
Data Retention Current
V
IN
> (V
CC
- 0.2V)
Chip Deselect to Data
Retention Time
Operation Recovery Time
V
CC
= 3V
I
CCDR
t
CDR
t
R
0
5
200
CONDITIONS
CE\ > (V
CC
- 0.2V)
V
CC
= 2V
SYMBOL
V
DR
I
CCDR
MIN
2
MAX
100
UNITS
V
µA
µA
ns
ms
4
4, 10
NOTES
AS5C4009
Rev. 5.1 6/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
AUSTIN [ AUSTIN SEMICONDUCTOR ]
