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AS5C512K8ECJ-17/XT 参数 Datasheet PDF下载

AS5C512K8ECJ-17/XT图片预览
型号: AS5C512K8ECJ-17/XT
PDF下载: 下载PDF文件 查看货源
内容描述: 512K ×8 SRAM高速SRAM和革命引脚 [512K x 8 SRAM HIGH SPEED SRAM with REVOLUTIONARY PINOUT]
分类和应用: 静态存储器
文件页数/大小: 17 页 / 229 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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SRAM  
AS5C512K8  
Austin Semiconductor, Inc.  
AC TEST CONDITIONS  
Input pulse levels ...................................................... Vss to 3.0V  
Input rise and fall times ......................................................... 3ns  
Input timing reference levels ............................................... 1.5V  
Output reference levels ........................................................ 1.5V  
Output load ................................................. See Figures 1 and 2  
167 ohms  
167 ohms  
Q
Q
1.73V  
1.73V  
C=30pF  
C=5pF  
Fig. 2 Output Load  
Equivalent  
Fig. 1 Output Load  
Equivalent  
NOTES  
1. All voltages referenced to VSS (GND).  
2. -2V for pulse width < 20ns  
9. Device is continuously selected. Chip enables and  
output enables are held in their active state.  
10. Address valid prior to, or coincident with, latest  
occurring chip enable.  
11. RC = Read Cycle Time.  
12. Chip enable and write enable can initiate and  
terminate a WRITE cycle.  
13. Output enable (OE\) is inactive (HIGH).  
14. Output enable (OE\) is active (LOW).  
15. ASI does not warrant functionality nor reliability of  
any product in which the junction temperature  
exceeds 150°C. Care should be taken to limit power to  
acceptable levels.  
3. ICC is dependent on output loading and cycle rates.  
4. This parameter is guaranteed but not tested.  
5. Test conditions as specified with the output loading  
as shown in Fig. 1 unless otherwise noted.  
6. tLZCE, tLZWE, tLZOE, t HZCE, tHZOE and tHZWE  
are specified with CL = 5pF as in Fig. 2. Transition is  
measured 200mV from steady state voltage.  
7. At any given temperature and voltage condition,  
t
tHZCE is less thantLZCE, and HZWE is less than  
t
tLZWE.  
8. WE\ is HIGH for READ cycle.  
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)  
DESCRIPTION  
CONDITIONS  
CE\ > VCC -0.2V  
IN > VCC -0.2 or 0.2V  
Vcc = 2.0V  
SYM  
MIN MAX UNITS NOTES  
Vcc for Retention Data  
VDR  
2
V
V
Data Retention Current  
Chip Deselect to Data  
Operation Recovery Time  
800  
uA  
ns  
ICCDR  
tCDR  
tR  
0
4
10  
ms  
4, 11  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
AS5C512K8  
Rev. 7.0 05/08  
5