SRAM
AS5C512K8
Austin Semiconductor, Inc.
LOW VCC DATA RETENTION WAVEFORM
DATA RETENTION MODE
VCC
4.5V
4.5V
VDR>2V
tCDR
tR
VIH-
CE\
VDR
VIL-
READ CYCLE NO. 18, 9
(Address Controlled, CE\ = OE\ = VIL, WE\ = VIH)
tRC
ADDRESS
VALID
tAA
tOH
I/O, DATAIN
& OUT
Previous Data Valid
Data Valid
READ CYCLE NO. 2 2
(WE\ = VIH)
tRC
ADDRESS
CE\
tAOE
tHZOE
tLZOE
tLZCE
tACE
tHZCE
I/O, DATAIN
& OUT
High-Z
Data Valid
tPU
tPD
Icc
Don’t Care
Undefined
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5C512K8
Rev. 7.0 05/08
6