PRELIMINARY
SPECIFICATION
EEPROM
AS8ERLC128K32
Austin Semiconductor, Inc.
Data Protection Cont.
a. Protection by RES\
The unprogrammable state can be realized by the
CPU's reset signal inputs directly to the EEPROM's RES pin.
To program data in the SDP enable mode, 3 bytes code must
be input before write data. This 4th cycle during write is
required to initiate the SDP and physically writes the address
and data. While in SDP the entire array is protected in which
writes can only occur if the exact SDP sequence is
re-executed or the unprotect sequence is executed.
The SDP is disabled by inputting the 6 bytes code in
Chart 2. Note that, if data is input in the SDP disable cycle,
data can not be written.
RES should be kept VSS level during VCC on/off.
The EEPROM brakes off programming operation
when RES becomes low, programming operation doesn't fin-
ish correctly in case that RES falls low during programming
operation. RES should be kept high for 10ms after the last
data inputs. See the timing diagram below.
The software data protection is not enabled at the
shipment.
3. Software data protection
NOTE: These are some differences between ASI's
and other company's for enable/disable sequence of software
data protection. If these are any questions, please contact ASI.
To prevent unintentional programming, this device
has the software data protection (SDP) mode. The SDP is
enabled by inputting the 3 bytes code and write data in
Chart 1. SDP is not enabled if only the 3 bytes code is input.
PROTECTION BY RES\
VCC
RES\
Program inhibit
Program inhibit
WE\ or CE\
100µ min
1µ min
10 ms min
CHART 1
CHART 2
Address
5555
Data
(each Byte)
AA
Address
Data
(each Byte)
AA
5555
AAAA or 2AAA
5555
AAAA or 2AAA
5555
55
80
AA
55
20
55
A0
5555
Write Address
Write Data}
Normal data input
AAAA or 2AAA
5555
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8ERLC128K32
Rev. 1.9 06/06
12
AUSTIN [ AUSTIN SEMICONDUCTOR ]
