AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
Table 2
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
A19
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A18
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A17
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A16
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A15
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A14
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A13
X
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
AS8FLC1M32
Sector Size
(Kbytes)
16
8
8
32
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
FLASH
Program and Erase Operation Status
During an ERASE or PROGRAM operation, the system may
check the status of the operation by reading the status bits on
each of the seven data I/O bits within each byte of the MCM
FLASH array. Standard READ cycle timings and ICC read
specifications apply. Refer to “Write Operation Status” for
more information, and to “AC Characteristics” for timing
specifications.
The AUTOMATIC SLEEP mode is independent of the CSx\,
WEx\ and OE\ control signals. Standard address access timings
provide new data when addresses are changed. While in sleep
mode, output data is latched and always available to the system.
ICC5 in the “DC Characteristics Table represents the
AUTOMATIC SLEEP mode current usage.
RESET\: Hardware Reset Pin
The RESET\ pin provides a hardware method of resetting the
device to reading array data. When the RESET\ pin is driven
low for at least a period of tRP, the device immediately terminates
any operation in progress, tristates all output pins, and ignores
all READ/WRITE commands for the duration of the RESET\
pulse. The device also resets the internal state machine to
reading array data. The operation that was interrupted should
be reinitiated once the device is ready to accept another
command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET\ pulse. When
RESET\ is held at VSS+/-0.3v, the device draws CMOS
STANDBY current (ICC4). If RESET\ is held at VIL but not
within the limits of VCC +/- 0.3v, the MCM Array will be in
STANDBY, but current limits will be higher than those listed
under ICC4.
The RESET\ pin may be tied to the system reset circuitry. A
system reset would thus also reset the FLASH array, enabling
the system to read the boot-up firmware code from the boot
block area of the memory.
Standby Mode
When the system is not READING or WRITING to the device,
it can place the device in the standby mode to save on power
consumption.
The device enters the CMOS STANDBY mode when the CSx\
and RESET\ pins are held at VCC+/-0.3v. If CSx\ and RESET\
are held at VIH, but not within VCC+/-0.3v, the device will be in
STANDBY mode but at levels higher than achievable in full
CMOS STANDBY. The device requires standard access time
(tCE) for read access when the device is in either of these
STANDBY modes, before it is ready to READ data.
If the device is deselected during ERASURE or
PROGRAMMING, the device draws active current until the
operation is completed.
In the DC Characteristics table, ICC3 and ICC4 represent the
STANDBY MODE currents.
Automatic Sleep Mode
The AUTOMATIC SLEEP mode minimizes FLASH device
energy consumption. The device automatically enables this
mode when addresses remain stable for tACC + 30ns.
AS8FLC1M32B
Rev. 3.3 05/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
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