DRAM
Austin Semiconductor, Inc.
NOTES:
1. All voltages referenced to Vss.
2. This parameter is sampled, not 100% tested. Capacitance
is measured with Vcc=5V, f=1 MHz at less than 50mVrms,
T
A
= 25°C ±3°C, Vbias = 2.4V applied to each input and
output individually with remaining inputs and outputs open.
3. Icc is dependent on cycle rates.
4. Icc is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle time and
the output open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate cycle
time at which proper operation over the full temperature range
(-55°C < T
A
< 125°C) is assured.
7. An initial pause of 100µs is required after power-up
followed by eight RAS\ refresh cycles (RAS\-ONLY or CBR
with WE\ HIGH) before proper device operation is assured.
The eight RAS\ cycle wake-up should be repeated any time
the 16ms refresh requirement is exceeded.
8. AC characteristics assume t
T
= 5ns.
9. V
IH
(MIN) and V
IL
(MAX) are reference levels for
measuring timing of input signals. Transition times are
measured between V
IH
and V
IL
(or between V
IL
and V
IH
).
10. In addition to meeting the transition rate specification, all
input signals must transit between V
IH
and V
IL
(or between
V
IL
and V
IH
) in a monotonic manner.
11. If CAS\ = V
IH
, data outputs (DQs) are High-Z.
12. If CAS\ = V
IL
, data outputs (DQs) may contain data from
the last valid READ cycle.
13. Measured with a load equivalent to two TTL gates and
100pF.
14. Assumes that t
RCD
< t
RCD
(MAX). If t
RCD
is greater than
the maximum recommended value shown in this table, t
RAC
will increase by the amount that t
RCD
exceeds the value shown.
15. Assumes that t
RCD
> t
RCD
(MAX)
16. If CAS\ is LOW at the falling edge of RAS\, DQs will be
maintained from the previous cycle. To initiate a new cycle
and clear the data out buffer, CAS\ must be pulsed HIGH for
t
CPN
.
17. Operation within the t
RCD
(MAX) limit ensures that t
RAC
(MAX) can be met. t
RCD
(MAX) is specified as a reference
point only; if t
RCD
is greater than the specified t
RCD
(MAX)
limit, then access time is controlled exclusively by t
CAC
.
18. Operation within the t
RAD
(MAX) limit ensures that t
RCD
(MAX) can be met. t
RAD
(MAX) is specified as a reference
point only; if t
RAD
is greater than the specified t
RAD
(MAX)
limit, then access time is controlled exclusively by t
AA
.
19. Either t
RCH
or t
RRH
must be satisfied for a READ cycle.
20. t
OFF
(MAX) defines the time at which the output achieves
the open circuit conditions and is not referenced to V
OH
or
V
OL
.
21. t
WCS
, t
RWD
, t
AWD
, and t
CWD
are not restrictive operating
parameters. t
WCS
applies to EARLY-WRITE cycles. t
RWD
,
t
AWD
, and t
CWD
apply to READ-MODIFY-WRITE cycles.
If t
WCS
> t
WCS
(MIN), the cycle is an EARLY-WRITE cycles
and the data output will remain an open circuit throughout the
entire cycle. If t
RWD
> t
RWD
(MIN), t
AWD
> t
AWD
(MIN) and
t
CWD
> t
CWD
(MIN), the cycle is a READ-MODIFY-WRITE
and the data output will contain data read from the selected
cell. If neither of the above conditions is met, the state of the
data out is indeterminate. OE\ held HIGH and WE\ taken LOW
after CAS\ goes LOW results in a LATE-WRITE (OE\
controlled) cycle. t
WCS
, t
RWD
, t
CWD
, and t
AWD
are not
applicable in a LATE-WRITE cycle.
22. These parameters are referenced to CAS\ leading edge in
EARLY-WRITE cycle and WE\ leading edge in LATE-WRITE
cycles and WE\ leading edge in LATE-WRITE or
READ-MODIFY-WRITE cycle.
23. If OE\ is tied permanently LOW, LATE-WRITE or
READ-MODIFY-WRITE operations are not possible.
24. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE\=LOW and OE\=HIGH.
25. t
WTS
and t
WTH
are setup and hold specifications for the
WE\ pin being held LOW to enable the JEDEC test mode (with
CBR timing constraints). These two parameters are the
inverts of t
WRP
and t
WRH
in the CBR REFRESH cycle.
26. LATE-WRITE and READ-MODIFY-WRITE cycles must
have both t
OD
and t
OEH
met (OE\ HIGH during WRITE cycle)
in order to ensure that the output buffers will be open during
the WRITE cycle. The DQs will provide the previously read
data if CAS\ remains LOW and OE\ is taken back LOW after
t
OEH
is met. If CAS\ goes HIGH prior to OE\ going back LOW,
the DQs will remain open.
27. The DQs open during READ cycles once t
OD
or t
OFF
occur. If CAS\ goes HIGH first, OE\ becomes a “don’t care.”
If OE\ goes HIGH and CAS\ stays LOW, OE\ is not a “don’t
care;” and the DQs will provide the previously read data if
OE\ is taken back LOW (while CAS\ remains LOW).
28. JEDEC test mode only.
MT4C4001J
MT4C4001J
Rev. 1.5 10/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
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