SRAM
Austin Semiconductor, Inc.
AC TEST CONDITIONS
Input pulse levels ................................... Vss to 3.0V
Input rise and fall times ....................................... 5ns
Input timing reference levels ............................. 1.5V
Output reference levels ..................................... 1.5V
Output load .............................. See Figures 1 and 2
MT5C1005
167Ω
Q
30pF
V
TH
= 1.73V Q
167Ω
5pF
V
TH
= 1.73V
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
NOTES
1.
2.
3.
All voltages referenced to V
SS
(GND).
-3V for pulse width < 20ns
I
CC
is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f =
1
Hz.
t
RC (MIN)
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6. Minimum of 5pF for t
EHQZ
, t
OHQZ
, t
ELQX
, t
OLQX
,
and t
WHQX
.
7.
At any given temperature and voltage condition,
t
HZCE is less than
t
LZCE, and
t
HZWE is less than
t
LZWE and
t
HZOE is less than
t
LZOE.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11.
t
RC = Read Cycle Time.
12. Chip enable (CE\) and write enable (WE\) can initiate and
terminate a WRITE cycle.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
V
CC
for Retention Data
CE\ > (V
CC
-0.2V)
and
V
IN
> (V
CC
-0.2V)
or < 0.2V
CONDITIONS
SYM
V
DR
MIN
2
MAX
UNITS NOTES
V
Data Retention Current
V
CC
= 2V
I
CCDR
5
mA
Chip Deselect to Data
Retention Time
Operation Recovery Time
t
CDR
t
R
0
t
RC
--
ns
ns
4
4, 11
LOW Vcc DATA RETENTION WAVEFORM
V
CC
t
DATA RETENTION MODE
4.5V
CDR
V
DR
V
DR
> 2V
4.5V
t
R
MT5C1005
Rev. 3.2 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
432
4321
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1
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21
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3
CE\
V
IH
V
IL
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DON’T CARE
UNDEFINED
AUSTIN [ AUSTIN SEMICONDUCTOR ]
