MT5C1008DCJ-45/883C 参数 Datasheet PDF下载

SRAM

Austin Semiconductor, Inc.

FUNCTIONAL BLOCK DIAGRAM

V

CC

GND

MT5C1008

A

A

A

A

A

A

A

A

A

ROW DECODER

DQ8

I/O CONTROL

1,048,576-BIT

MEMORY ARRAY

DQ1

(LSB)

CE1\

CE2

COLUMN DECODER

(LSB)

OE\

WE\

POWER

DOWN

A A A A A A A A

NOTE:

The two least significant row address bits (A8 and A6) are encoded using gray code.

TRUTH TABLE

MODE

STANDBY

STANDBY

READ

READ

WRITE

OE\

X

X

L

H

X

CE1\

H

X

L

L

L

CE2

X

L

H

H

H

WE\

X

X

H

H

L

DQ

HIGH-Z

HIGH-Z

Q

HIGH-Z

D

POWER

STANDBY

STANDBY

ACTIVE

ACTIVE

ACTIVE

MT5C1008

Rev. 6.5 7/02

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

2