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MT5C1008DCJ-45/883C 参数 Datasheet PDF下载

MT5C1008DCJ-45/883C图片预览
型号: MT5C1008DCJ-45/883C
PDF下载: 下载PDF文件 查看货源
内容描述: 与双芯片128K ×8 SRAM启用可作为军用规格 [128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS]
分类和应用: 静态存储器
文件页数/大小: 17 页 / 185 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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SRAM
Austin Semiconductor, Inc.
+5V
AC TEST CONDITIONS
Input pulse levels ................................... Vss to 3.0V
Input rise and fall times ....................................... 5ns
Input timing reference levels ............................. 1.5V
Output reference levels ..................................... 1.5V
Output load .............................. See Figures 1 and 2
MT5C1008
+5V
480
480
Q
255
5 pF
Q
255
30
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
NOTES
1.
2.
3.
All voltages referenced to V
SS
(GND).
-2V for pulse width < 20ns
I
CC
is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f =
1
Hz.
t
RC (MIN)
This parameter is guaranteed but not tested.
Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
t
LZCE,
t
LZWE,
t
LZOE,
t
HZCE,
t
HZOE and
t
HZWE
are specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV typical from steady state voltage,
allowing for actual tester RC time constant.
7.
8.
9.
10.
11.
12.
13.
4.
5.
6.
At any given temperature and voltage condition,
t
HZCE is less than
t
LZCE, and
t
HZWE is less than
t
LZWE and
t
HZOE is less than
t
LZOE.
WE\ is HIGH for READ cycle.
Device is continuously selected. Chip enables and
output enables are held in their active state.
Address valid prior to, or coincident with, latest
occurring chip enable.
t
RC = Read Cycle Time.
CE2 timing is the same as CE1\ timing. The
waveform is inverted.
Chip enable (CE1\, CE2) and write enable (WE\) can
initiate and terminate a WRITE cycle.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
V
CC
for Retention Data
CE\ > (V
CC
- 0.2V)
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
V
IN
> (V
CC
- 0.2V)
or < 0.2V, f=0
V
CC
= 2V
I
CCDR
1.0
mA
CONDITIONS
SYMBOL
V
DR
MIN
2
MAX
---
UNITS NOTES
V
t
CDR
t
R
0
t
RC
---
ns
ns
4
4, 11
LOW Vcc DATA RETENTION WAVEFORM
V
CC
t
DATA RETENTION MODE
4.5V
CDR
V
DR
V
DR
> 2V
4.5V
t
R
<V
SS
+ 0.2V
MT5C1008
Rev. 6.5 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
432
4321
4321
1
4321
CE2
V
IH
V
IL
321
21
321
321
3
CE1\
V
IH
V
IL
487
337
4226
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87
4226
331154321
876
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432
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DON’T CARE
UNDEFINED