SRAM
Austin Semiconductor, Inc.
+5V
AC TEST CONDITIONS
Input pulse levels ...................................... Vss to 3.0V
Input rise and fall times ......................................... 5ns
Input timing reference levels ................................ 1.5V
Output reference levels ....................................... 1.5V
Output load ................................. See Figures 1 and 2
MT5C6405
+5V
480
480
Q
255
5 pF
Q
255
30pF
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
NOTES
1.
2.
3.
All voltages referenced to V
SS
(GND).
-3V for pulse width < 20ns
I
CC
is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f =
1
Hz.
t
RC (MIN)
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6. t
HZCE
, t
HZOE
and t
HZWE
are specified with CL = 5pF as
in Fig. 2. Transition is measured ±200mV typical from
steady state voltage, allowing for actual tester RC time
constant.
At any given temperature and voltage condition,
t
HZCE
is less than t
LZCE
, and t
HZWE
is less than t
LZWE
.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11.
t
RC = Read Cycle Time.
12. CE2 timing is the same as CE1\ timing. The waveform
is inverted.
7.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
V
CC
for Retention Data
CE\ > (V
CC
- 0.2V)
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
V
IN
> (V
CC
- 0.2V)
or < 0.2V
V
CC
= 2V
I
CCDR
1
mA
CONDITIONS
SYM
V
DR
MIN
2
MAX
---
UNITS
V
NOTES
t
CDR
t
R
0
t
RC
---
ns
ns
4
4, 11
LOW Vcc DATA RETENTION WAVEFORM
V
CC
t
CDR
DATA RETENTION MODE
4.5V
V
DR
> 2V
4.5V
t
R
CE\
MT5C6405
Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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UNDEFINED