Powering the Device
Ground Connection
AGND and DGND must both be set to 0V and preferably
star-connected to a central power source as shown in
the application diagram. A potential difference between
AGND and DGND may cause the ESD diodes to turn on
inadvertently.
Application Diagrams
HOST
SYSTEM
10k
DVDD
10k
10k
10k
XRST
SDA
SCL
HOST
SYSTEM
AVDD
A1
Voltage
Regulator
AGND
A2, A3,
D2
DGND
C2
DVDD
D1
Voltage
Regulator
Star-connected ground
D4
C4
C3
XRST
SDASLV
SCLSLV
A4
SLEEP
Pin Information
Pin
A1
A2
A3
A4
Name
AVDD
AGND
AGND
SLEEP
Type
Power
Ground
Ground
Input
Description
Analog power pin.
Tie to analog ground.
Tie to analog ground.
When SLEEP=1, the device goes into sleep mode. In sleep mode, all analog circuits are
powered down and the clock signal is gated away from the core logic resulting in very
low current consumption.
No connect. Leave floating.
No connect. Leave floating.
No connect. Leave floating.
No connect. Leave floating.
No connect. Leave floating
Tie to digital ground.
SDASLV and SCLSLV are the serial interface communications pins. SDASLV is the bidi-
rectional data pin and SCLSLV is the interface clock. A pull-up resistor should be tied to
SDASLV because it goes tri-state to output logic 1.
Digital power pin.
Tie to analog ground.
No connect. Leave floating.
Global, asynchronous, active-low system reset. When asserted low, XRST resets all regis-
ters. Minimum reset pulse low is 1 us and must be provided by external circuitry.
B1
B2
B3
B4
C1
C2
C3
C4
NC
NC
NC
NC
NC
DGND
SCLSLV
SDASLV
No connect
No connect
No connect
No connect
No connect
Ground
Input
Input/
Output(tri-state
high)
Power
Ground
No connect
Input
D1
D2
D3
D4
DVDD
AGND
NC
XRST
1
AVAGO [ AVAGO TECHNOLOGIES LIMITED ]
