Serial Interface Reference
Description
The programming interface to the ADJD-S312 is a 2-wire
serial bus. The bus consists of a serial clock (SCL) and a
serial data (SDA) line. The SDA line is bi-directional on
ADJD-S312 and must be connected through a pull-up
resistor to the positive power supply. When the bus is
free, both lines are HIGH.
The 2-wire serial bus on ADJD-S312 requires one device
to act as a master while all other devices must be slaves.
A master is a device that initiates a data transfer on the
bus, generates the clock signal and terminates the data
transfer while a device addressed by the master is called a
slave. Slaves are identified by unique device addresses.
Both master and slave can act as a transmitter or a receiv-
er but the master controls the direction for data transfer.
A transmitter is a device that sends data to the bus and a
receiver is a device that receives data from the bus.
The ADJD-S312 serial bus interface always operates
as a slave transceiver with a data transfer rate of up to
100kbit/s.
START/STOP Condition
The master initiates and terminates all serial data trans-
fers. To begin a serial data transfer, the master must send
a unique signal to the bus called a START condition. This
is defined as a HIGH to LOW transition on the SDA line
while SCL is HIGH.
The master terminates the serial data transfer by sending
another unique signal to the bus called a STOP condition.
This is defined as a LOW to HIGH transition on the SDA
line while SCL is HIGH.
The bus is considered to be busy after a START (S) condi-
tion. It will be considered free a certain time after the
STOP (P) condition. The bus stays busy if a repeated
START (Sr) is sent instead of a STOP condition.
The START and repeated START conditions are function-
ally identical.
Data Transfer
The master initiates data transfer after a START condition.
Data is transferred in bits with the master generating one
clock pulse for each bit sent. For a data bit to be valid, the
SDA data line must be stable during the HIGH period of
the SCL clock line. Only during the LOW period of the SCL
clock line can the SDA data line change state to either
HIGH or LOW.
SDA
SCL
Data valid
Figure 2: Data Bit Transfer
Data change
The SCL clock line synchronizes the serial data transmis-
sion on the SDA data line. It is always generated by the
master. The frequency of the SCL clock line may vary
throughout the transmission as long as it still meets the
minimum timing requirements.
The master by default drives the SDA data line. The slave
drives the SDA data line only when sending an acknowl-
edge bit after the master writes data to the slave or when
the master requests the slave to send data.
The SDA data line driven by the master may be imple-
mented on the negative edge of the SCL clock line. The
master may sample data driven by the slave on the posi-
tive edge of the SCL clock line. Figure shows an example
of a master implementation and how the SCL clock line
and SDA data line can be synchronized.
SDA data sampled on the
positive edge of SCL
SDA
SCL
SDA data driven on the
negative edge of SCL
Figure 3: Data Bit Synchronization
SDA
SCL
S
START condition
P
STOP condition
Figure 1: START/STOP Condition
AVAGO [ AVAGO TECHNOLOGIES LIMITED ]
