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ATF-521P8-TR2 参数 Datasheet PDF下载

ATF-521P8-TR2图片预览
型号: ATF-521P8-TR2
PDF下载: 下载PDF文件 查看货源
内容描述: 高线性度增强模式[ 1 ]赝2×2 mm2的LPCC [ 3 ]包 [High Linearity Enhancement Mode[1] Pseudomorphic 2x2 mm2 LPCC[3] Package]
分类和应用: 晶体晶体管光电二极管放大器PC
文件页数/大小: 23 页 / 304 K
品牌: AVAGO [ AVAGO TECHNOLOGIES LIMITED ]
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ATF-521P8 Absolute Maximum Ratings
[1]
Symbol
V
DS
V
GS
V
GD
I
DS
I
GS
P
diss
P
in max.
T
CH
T
STG
θ
ch_b
Parameter
Drain – Source Voltage
[2]
Gate –Source Voltage
[2]
Gate Drain Voltage
[2]
Drain Current
[2]
Gate Current
Total Power Dissipation
[3]
RF Input Power
Channel Temperature
Storage Temperature
Thermal Resistance
[4]
Units
V
V
V
mA
mA
W
dBm
°C
°C
°C/W
Absolute
Maximum
7
‑5 to 1
‑5 to 1
500
46
1.5
27
150
‑65 to 150
45
Notes:
1. Operation of this device in excess of any one of these parameters may cause permanent damage.
2. Assumes DC quiescent conditions.
3. Board (package belly) temperatureT
B
is 25°C. Derate 22 mW/°C for T
B
> 83°C.
4. Channel to board thermal resistance measured using 150°C Liquid Crystal Measurement method.
5. Device can safely handle +27dBm RF Input Power provided IGS is limited to 46mA. IGS at P1dB drive level is bias circuit dependent.
Product Consistency Distribution Charts
[5, 6]
600
500
400
I
DS
(mA)
0.8V
0.7V
180
150
120
90
Vgs = 0.6V
Stdev = 0.19
150
Cpk = 0.86
Stdev = 1.32
120
300
200
100
0
-3 Std
+3 Std
90
-3 Std
+3 Std
60
60
30
0
6
8
30
0.5V
0.4V
0
2
4
V
DS
(V)
0
0.5
1
1.5
NF (dB)
2
2.5
3
0
37
39
41
43
OIP3 (dBm)
45
47
49
Figure 1. Typical I-V Curves.
(V
GS
= 0.1 V per step)
180
150
120
90
60
30
0
-3 Std
+3 Std
Cpk = 2.13
Stdev = 0.21
Figure 2. NF @ 2 GHz, 4.5 V, 200 mA.
Nominal = 1.5 dB.
300
250
200
150
100
50
0
-3 Std
+3 Std
Figure 3. OIP3 @ 2 GHz, 4.5 V, 200 mA.
Nominal = 41.9 dBm, LSL = 38.5 dBm.
Cpk = 4.6
Stdev = 0.11
15
16
17
GAIN (dB)
18
19
25
25.5
26
26.5
27
27.5
P1dB (dBm)
Figure 4. Gain @ 2 GHz, 4.5 V, 200 mA.
Nominal = 17.2 dB, LSL = 15.5 dB,
USL = 18.5 dB.
Figure 5. P1dB @ 2 GHz, 4.5 V, 200 mA.
Nominal = 26.5 dBm, LSL = 25 dBm.
Notes:
5. Distribution data sample size is 500 samples taken from 5 different wafers. Future wafers allocated to this product may have nominal values
anywhere between the upper and lower limits.
6. Measurements are made on production test board, which represents a trade‑off between optimal OIP3, P1dB and VSWR. Circuit losses have
been de‑embedded from actual measurements.
2