AZ100LVEL16VT
LOGIC DIAGRAMS AND PINOUTS FOR 2x2mm PACKAGE
4mA
Q
D
D
470
Ω
470
Ω
MLP 8, 2x2mm
V
EE
Q
HG
Q
HG
D
D
1
2
AZ100LVEL16VTNA
8
7
Q
V
CC
Q
HG
Q
HG
V
BB
EN
V
EE
V
BB
3
6
5
TOP VIEW
MLP 8, 2x2mm
AZ100LVEL16VTNA
4mA
EN
4
V
EE
¯¯¯ operation follows PECL functionality.
EN
D
Q
HG
See Timing Diagram above.
470Ω
Q
HG
V
BB
EN
Q
Bottom
1
Center Pad is the V
EE
8 Q
AZ100LVEL16VTNB
return.
D
V
BB
EN
V
EE
2
3
4
7
6
5
V
CC
Q
HG
Q
HG
MLP 8, 2x2mm
MLP 8, 2x2mm
AZ100LVEL16VTNB
TOP VIEW
¯¯¯ operation follows PECL functionality.
EN
See Timing Diagram above.
Bottom Center Pad may be left open
or tied to V
EE
. Pin 4 is the V
EE
return.
April 2007 * REV - 9
www.azmicrotek.com
8