AZ100LVEL16VT
LOGIC DIAGRAMS AND PINOUTS FOR 2x2mm PACKAGE
4mA
Q
D
470
Ω
MLP 8, 2x2mm
V
EE
Q
HG
Q
HG
D
V
BB
EN
V
EE
1
2
3
4
AZ100LVEL16VTNC 8
7
6
5
Q
V
CC
Q
HG
Q
HG
V
BB
EN
CMOS / TTL
THRESHOLD
MLP 8, 2x2mm
AZ100LVEL16VTNC
TOP VIEW
EN operation follows CMOS/TTL
functionality. See Timing Diagram above.
Bottom Center Pad may be left open
or tied to V
EE
. Pin 4 is the V
EE
return.
4mA
MLP 8, 2x2mm
V
EE
Q
HG
Q
HG
Q
D
D
V
BB
EN
470
470
D
D
1
2
AZ100LVEL16VTND
8
7
Q
V
CC
Q
HG
Q
HG
V
EE
6
5
TOP VIEW
V
BB
3
EN
4
CMOS / TTL
THRESHOLD
MLP 8, 2x2mm
AZ100LVEL16VTND
EN operation follows CMOS/TTL
functionality. See Timing Diagram above.
Bottom Center Pad is the V
EE
return.
April 2007 * REV - 9
www.azmicrotek.com
9