AZ100LVEL16VT
¯
Outputs Q
HG
and Q
HG
each have an optional on-chip pull-down current source of 10 mA. When pad/pin V
EEP
is
left open (NC), the output current sources are disabled and the Q
HG
/Q
HG
operate as standard PECL/ECL. When V
EEP
¯
is connected to V
EE
, the current sources are activated. The Q
HG
/Q
HG
pull-down current can be decreased, by using a
¯
resistor to connect V
EEP
to V
EE
. (See graph on page 5.)
MLP 8, 2x2 mm Package, VTNA, VTNB, VTNC & VTND Versions
All MLP 8, 2x2mm versions of the AZ100LVEL16VT provide an enable input that allows continuous oscillator
operation. VTNA and VTNB utilize an enable (EN) that operates in the PECL/ECL mode. When the EN input is
¯¯
¯¯
LOW, the Q and Q
HG
/Q
HG
outputs follow the data inputs. When EN is HIGH, the Q
HG
output is forced high and the
¯
¯
¯¯
Q
HG
output is forced low. VTNC and VTND utilize an enable (EN) that operates in the CMOS/TTL mode. When the
¯
EN input is HIGH, the Q and Q
HG
/Q
HG
outputs follow the data inputs. When EN is LOW, the Q
HG
output is forced
¯
¯
high and the Q
HG
output is forced low.
¯
For VTNA and VTND, both D and D inputs are brought out and tied to the V
BB
pin through 470
Ω
internal bias
¯
resistors. In VTNB and VTNC, the D input is internally tied directly to the V
BB
pin and the D input is tied to the V
BB
¯
pin through a 470
Ω
internal bias resistor. Bypassing V
BB
to ground with a 0.01
μF
capacitor is recommended.
All MLP 8, 2x2mm versions (VTNA, VTNB, VTNC & VTND) have the Q, Q
HG
, and Q
HG
current sources
¯
disabled, while the Q output operates with a 4 mA current source to V
EE
.
¯
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
ENABLE TRUTH TABLE
MLP 16 (VTL) or DIE (VTX)
EN-SEL
EN
Q/Q Q
HG
¯
NC
PECL Low, V
EE
or NC
Data Data
NC
PECL High or V
CC
Data High
V
EE
*
Data High
CMOS Low or V
EE
V
EE
*
CMOS High or V
CC
Data Data
Data High
V
EE
*
NC, no external pull-up
Data Data
V
EE
*
NC, with
≤20kΩ
to V
CC
*Connections to V
CC
or V
EE
must be less than 1Ω.
PIN DESCRIPTION
PIN
D/D
¯
Q/Q
¯
Q
HG
/Q
HG
¯
V
BB
EN-SEL
EN/EN
¯¯
CS-SEL
V
EEP
V
EE
V
CC
FUNCTION
Data Inputs
Data Outputs
Data Outputs w/High Gain
Reference Voltage Output
Selects Enable Logic
Enable Input
Selects Q and Q Current Source Magnitude
¯
Optional Q
HG
and Q
HG
Current Sources
¯
Negative Supply
Positive Supply
Q
HG
¯
Data
Low
Low
Data
Low
Data
4mA EA.
Q
Q
D
D
470
Ω
470
Ω
CS-SEL
Q
HG
Q
HG
10mA EA.
V
BB
EN
CMOS / TTL
THRESHOLD
MLP 16 (VTL) or DIE (VTX)
V
EEP
V
EE
EN-SEL
CURRENT SOURCE TRUTH TABLE
MLP 16 (VTL) or DIE (VTX)
CS-SEL
Q
Q
¯
NC
4mA typ.
4mA typ.
V
EE
*
8mA typ.
8mA typ.
V
CC
*
0
4mA typ.
*Connections to V
CC
or V
EE
must be less than 1Ω.
April 2007 * REV - 9
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