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AZ100LVEL16VTL+ 参数 Datasheet PDF下载

AZ100LVEL16VTL+图片预览
型号: AZ100LVEL16VTL+
PDF下载: 下载PDF文件 查看货源
内容描述: ECL / PECL振荡器增益级和缓冲区,可选择启用 [ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable]
分类和应用: 振荡器
文件页数/大小: 13 页 / 216 K
品牌: AZM [ ARIZONA MICROTEK, INC ]
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AZ100LVEL16VT
100K PECL DC Characteristics
(V
EE
= GND, V
CC
= +5.0V)
Symbol
V
OH
V
OH
V
OL
V
IH
V
IL
V
BB
I
IL
I
IH
I
EE
1.
2.
3.
4.
5.
Characteristic
-40°C
Min
3955
3915
3075
Max
4165
4120
3445
Min
4005
3975
3100
0°C
Max
4165
4120
3338
Min
4005
3975
3100
25°C
Max
4165
4120
3338
Min
4005
3975
3100
3835
2000
3190
GND
3610
0.5
85°C
Max
4165
4120
3338
4120
V
CC
3525
800
3750
150
54
Unit
mV
mV
mV
mV
mV
mV
μA
μA
mA
Output HIGH Voltage
1,3
Output HIGH Voltage
1,5
Output LOW Voltage
1,3,5
Input HIGH Voltage
3835
4120
3835
4120
3835
4120
D/D, EN/EN (PECL)
1
¯
¯¯
EN (CMOS/TTL)
2000
V
CC
2000
V
CC
2000
V
CC
Input LOW Voltage
3190
3525
3190
3525
3190
3525
D/D, EN/EN (PECL)
1
¯
¯¯
EN (CMOS/TTL)
GND
800
GND
800
GND
800
1
Reference Voltage
3610
3750
3610
3750
3610
3750
Input LOW Current EN
4
0.5
0.5
0.5
Input HIGH Current EN
4
150
150
150
Power Supply Current
2
48
48
48
For supply voltages other that 5.0V, use the ECL table values and ADD supply voltage value.
Specified with V
EEP
and CS-SEL open for VTL and VTX. Subtract 4mA for VTNA, VTNB, VTNC & VTND.
Specified with V
EEP
and CS-SEL connected to V
EE
for VTL and VTX only.
Specified with EN-SEL open for VTL and VTX only.
¯
Specified with Q
HG
/Q
HG
connected with 50
to V
CC
–2V for VTNA, VTNB, VTNC & VTND.
AC Characteristics
(V
EE
= -3.0V to -5.5V; V
CC
= GND or V
EE
= GND; V
CC
= +3.0V to +5.5V)
Symbol
t
PLH
/ t
PHL
Characteristic
Min
-40°C
Typ
Max
Min
0°C
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
Max
Unit
ps
ps
mV
ps
Propagation Delay
400
400
400
430
(SE)
D to Q/Q Outputs
1
¯
¯
550
550
550
630
D to Q
HG
/Q
HG
Outputs
1
(SE)
2
t
SKEW
Duty Cycle Skew
(SE)
5
20
5
20
5
20
5
20
80
80
80
80
Minimum Input Swing
3
DIFF
V
PP
SE
160
160
160
160
1
Output Rise/Fall Times
100
260
100
260
100
260
100
260
t
r
/ t
f
(20% - 80%)
1.
For VTL and VTX, output specified with V
EEP
and CS-SEL connected to V
EE
with an AC coupled 50Ω load. For VTNA, VTNB, VTNC &
¯
VTND, AC coupled 50Ω on Q to V
CC
–2V and DC coupled 50Ω to V
CC
–2V on Q
HG
/Q
HG.
¯
2.
Duty cycle skew is the difference between a t
PLH
and t
PHL
propagation delay through a device.
3.
V
PP
is the minimum peak-to-peak input swing for which AC parameters guaranteed. The device has a voltage gain of
20 to Q/Q outputs and a
¯
¯
voltage gain of
100 to Q
HG
/Q
HG
outputs.
D
EN
EN
(VTL, VTX)
;
EN
(VTNA, VTNB)
(PECL)
(CMOS)
(VTL, VTX, VTNC, VTND)
Q
Q
Q
HG
Q
HG
TIMING DIAGRAM
April 2007 * REV - 9
www.azmicrotek.com
4