Arizona Microtek, Inc.
AZ100LVEL16VV
Dual Frequency PECL/ECL Oscillator
Gain Stage & Buffer with Enable
E
NGINEERING
N
OTES
The data inputs are selected with the select pin (SEL). When SEL is LOW or open (NC) data from the D0/D0 is selected.
¯¯
When SEL is HIGH data from the D1/D1 is selected. See Table 2 for data selection.
¯¯
The enable pin (EN) works with either data input pair. When EN is HIGH or open (NC), input data is passed to both sets
of outputs. When EN is LOW, the Q
HG
/Q
HG
outputs will be forced LOW/HIGH respectively, while input data will
¯
continue to be passed to the Q/Q outputs. The EN and SEL inputs can be driven with an ECL/PECL signal or a full supply
¯
swing CMOS type logic signal. See table 2 for enable operation.
Internal Input biasing is accomplished with a V
BB
and separate 470Ω bias resistors connecting each data input to V
BB
. The
V
BB
pin supports 1.5mA sink/source current and should be bypassed to ground with a 0.01µF capacitor.
Each Q/Q output has a 4 mA on-chip pull-down current source. External resistors may also be used to increase pull-down
¯
current of the Q/Q to a maximum of 25mA each (includes a 4 mA on-chip current source).
¯
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
Table 2 - Truth Table
EN
CS-SEL
Q
Q
¯
Q
HG
Q
HG
¯
High/Open
High/Open
Low
Low
Low/Open
High
Low/Open
High
D0/D0
¯¯
D1/D1
¯¯
D0/D0
¯¯
D1/D1
¯¯
D0/D0
¯¯
D1/D1
¯¯
D0/D0
¯¯
D1/D1
¯¯
D0/D0
¯¯
D1/D1
¯¯
Low
Low
D0/D0
¯¯
D1/D1
¯¯
High
High
D0
D1
EN
SEL
Q
Q
Q
HG
Q
HG
Figure 2 - Timing Diagram
+1-480-962-5881
3
May 2012, Rev 2.0
AZM [ ARIZONA MICROTEK, INC ]
