SYSTEM CLOCK
The system clock for PCM1717 must be either 256f
S
or
384f
S
, where f
S
is the audio sampling frequency (typically
32kHz, 44.1kHz, or 48kHz). The system clock is used to
operate the digital filter and the modulator.
The system clock can be either a crystal oscillator placed
between XTI (pin 1) and XTO (pin 20), or an external clock
input to XTI. If an external system clock is used, XTO is
open (floating). Figure 1 illustrates the typical system clock
connections.
PCM1717 has a system clock detection circuit which auto-
matically senses if the system clock is operating at 256f
S
or
384f
S
. The system clock should be synchronized with LRCIN
(pin 4) clock. LRCIN (left-right clock) operates at the
sampling frequency fs. In the event these clocks are not
synchronized, PCM1717 can compensate for the phase dif-
ference internally. If the phase difference between left-right
and system clocks is greater than 6 bit clocks (BCKIN), the
synchronization is performed internally. While the synchro-
nization is processing, the analog output is forced to a DC
level at bipolar zero. The synchronization typically occurs in
less than 1 cycle of LRCIN.
DATA INTERFACE FORMATS
Digital audio data is interfaced to PCM1717 on pins 4, 5,
and 6—LRCIN (left-right clock), DIN (data input) and
BCKIN (bit clock). PCM1717 can accept both normal and
I
2
S data formats. Normal data format is MSB first, two’s
complement, right-justified. I
2
S data is compatible with
Philips serial data protocol. In the I
2
S format, the data is 16-
or 18-bit, selectable by bit 0 on Register 3 (Software Control
Mode). In the Hardware Mode, PCM1717 can only function
with 16-bit normal data. Figures 5 through 9 illustrate timing
and input formats.
CLKO
CLKO
Internal System Clock
Internal System Clock
C
1
X’tal
XTI
External Clock
XTI
C
2
XTO
C
1
, C
2
= 10 to 20pF
PCM1717E
XTO
PCM1717E
EXTERNAL CLOCK INPUT
XTO pin = No Connection
CRYSTAL RESONATOR CONNECTION
FIGURE 1. Internal Clock Circuit Diagram and Oscillator Connection.
t
XTIH
1/256f
S
or 1/384f
S
64% OF V
DD
28% OF V
DD
t
XTIL
External System Clock High
External System Clock Low
t
XTIH
t
XTIL
10ns (min)
10ns (min)
FIGURE 2. External Clock Timing Requirements.
®
PCM1717
6
BURR-BROWN [ BURR-BROWN CORPORATION ]
