BS62LV1027
WRITE CYCLE 2
ADDRESS
t
CW
(11)
(1,6)
t
WC
CE1
(5)
CE2
(5)
t
AW
WE
t
AS
t
WHZ
D
OUT
(4,10)
t
CW
(11)
(2)
t
WP
t
WR2
(3)
t
OW
t
DW
t
DH
(8,9)
(7)
(8)
D
IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and
WE low. All signals must be active to initiate a write and any one signal can terminate a
write by going inactive. The data input setup and hold timing should be referenced to the
second transition edge of the signal that terminates the write.
3. t
WR
is measured from the earlier of CE1 or WE going high or CE2 going low at the end of
write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = V
IL
).
7. D
OUT
is the same phase of write data of this write cycle.
8. D
OUT
is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the
data input signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured
±
500mV from steady state with C
L
= 5pF.
The parameter is guaranteed but not 100% tested.
11. t
CW
is measured from the later of CE1 going low or CE2 going high to the end of write.
R0201-BS62LV1027
7
Revision 2.3
May.
2006
BSI [ BRILLIANCE SEMICONDUCTOR ]
