Data Sheet
Digital and Timing Electrical Characteristics
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 50 MSPS clock, 50% clock duty cycle,
-1 dBFS input signal, 5pF capacitive load, unless otherwise noted)
Symbol
Clock Inputs
Parameter
Duty Cycle
Compliance
Input Range
Input Common Mode Voltage
Input Capacitance
Conditions
Min
20
Typ
Max
80
Units
CDK2307
Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters
% high
mVpp
Vpp
CMOS, LVDS, LVPECL, Sine Wave
Differential input swing
Differential input swing, sine wave clock input
Keep voltages within ground and voltage of OVDD
Differential
From Power Down Mode to Active Mode
From Sleep Mode to Active
1
0.8
<0.5
12
5pF load on output bits
Relative to CLK_EXT
VOVDD ≥ 3.0V
VOVDD = 1.7V – 3.0V
VOVDD ≥ 3.0V
VOVDD = 1.7V – 3.0V
3
1
2
0.8
•
VOVDD
0
0
-10
-10
3
VOVDD-0.1
0.1
Post-driver supply voltage equal to pre-driver
supply voltage VOVDD = VDVDD
Post-driver supply voltage above 2.25V
(1)
10
5
0.8
0.2
•
VOVDD
10
10
10
6
400
1.6
0.3
2
900
20
VOVDD -0.3
V
pF
clk cycles
clk cycles
clk cycles
ns
psrms
clk cycles
ns
ns
V
V
V
V
µA
µA
pF
V
V
pF
pF
Timing
T
PD
T
SLP
T
OVR
T
AP
Start Up Time Active Mode
Start Up Time Mode
Out Of Range Recovery Time
Aperture Delay
Aperture Jitter
Pipeline Delay
Output Delay (see timing diagram)
Output Delay (see timing diagram)
ε
RMS
T
LAT
T
D
T
DC
Logic Inputs
V
HI
V
LI
I
HI
I
LI
C
I
High Level Input Voltage
Low Level Input Voltage
High Level Input Leakage Current
Low Level Input Leakage Current
Input Capacitance
High Level Output Voltage
Low Level Output Voltage
Max Capacitive Load
Logic Outputs
V
HO
V
LO
C
L
Note:
(1) The outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents
and resulting switching noise at a minimum.
Rev 2B
©2009 CADEKA Microcircuits LLC
www.cadeka.com
10
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
