Data Sheet
Electrical Characteristics - CDK2307D
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 80MSPS clock, 50% clock duty cycle,
-1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)
Symbol
Performance
Parameter
Conditions
F
IN
= 8MHz
Min
70.4
Typ
72
71.7
71.2
70.7
Max
Units
CDK2307
Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
bits
bits
bits
bits
dB
SNR
Signal to Noise Ratio
F
IN
= 20MHz
F
IN
= 30MHz
F
IN
≃
FS/2
F
IN
= 8MHz
69.5
F
IN
= 20MHz
F
IN
= 30MHz
F
IN
≃
FS/2
F
IN
= 8MHz
74
F
IN
= 20MHz
F
IN
= 30MHz
F
IN
≃
FS/2
F
IN
= 8MHz
-80
F
IN
= 20MHz
F
IN
= 30MHz
F
IN
≃
FS/2
F
IN
= 8MHz
-74
F
IN
= 20MHz
F
IN
= 30MHz
F
IN
≃
FS/2
F
IN
= 8MHz
11.3
F
IN
= 20MHz
F
IN
= 30MHz
F
IN
≃
FS/2
Signal crosstalk between channels, F
IN1
=
8MHz, F
IN0
= 9.9MHz
70.5
70.5
70.4
70.3
77
78
78
78
-95
-90
-90
-85
-77
-78
-78
-78
11.4
11.4
11.4
11.4
-95.0
SINAD
Signal to Noise and Distortion Ratio
SFDR
Spurious Free Dynamic Range
HD2
Second order Harmonic Distortion
HD3
Third order Harmonic Distortion
ENOB
Effective number of Bits
X
TALK
Crosstalk
Power Supply
AIDD
DIDD
Analog Supply Current
Digital Supply Current
Digital core supply
2.5V output driver supply, sine wave input,
F
IN
= 1MHz
2.5V output driver supply, sine wave input,
F
IN
= 1MHz, CLK_EXT disabled
OVDD = 2.5V, 5pF load on output bits,
F
IN
= 1MHz, CLK_EXT disabled
OVDD = 2.5V, 5pF load on output bits,
F
IN
= 1MHz, CLK_EXT disabled
Power Dissipation, Sleep mode one channel
Power Dissipation, Sleep mode both channels
80
65
39.7
6.0
9.4
7.7
71.5
30
101.5
9.1
66.4
24.1
mA
mA
mA
mA
mW
mW
mW
µW
mW
mW
MSPS
MSPS
OIDD
Output Driver Supply
Analog Power Dissipation
Digital Power Dissipation
Total Power Dissipation
Power Down Dissipation
Sleep Mode 1
Sleep Mode 2
Rev 2B
Clock Inputs
Max. Conversion Rate
Min. Conversion Rate
©2009 CADEKA Microcircuits LLC
www.cadeka.com
9
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