Data Sheet
The CDK3405 may also be operated with a single 75Ω
terminating resistor. To lower the output voltage swing
to the desired range, the nominal value of the resistor on
R
REF
should be doubled.
R, G, and B Current Outputs - IO
R
, IO
G
, IO
B
Current source outputs can drive VESA VSIS, and RS-
343A/SMPTE-170M compatible levels into doubly-termi-
nated 75Ω lines. Sync pulses can be added to the green
output. When SYNC is HIGH, the current added to IO
G
is:
IO
S
= 2.33 (V
REF
/ R
REF
)
Current-Setting Resistor - R
REF
Full-scale output current of each D/A converter is deter-
mined by the value of the resistor connected between
R
REF
and GND. Nominal value of R
REF
is found from:
R
REF
= 5.31 (V
REF
/I
FS
)
where I
FS
is the full-scale (white) output current (in amps)
from the D/A converter (without sync). Sync is 0.439 * I
FS
.
D/A full-scale (white) current may also be calculated from:
I
FS
= V
FS
/R
L
Where V
FS
is the white voltage level and R
L
is the total
resistive load (Ω) on each D/A converter. V
FS
is the blank
to full-scale voltage.
and GND. Voltage across R
SET
is the reference voltage,
V
REF,
which can be derived from either the 1.25 volt in-
ternal bandgap reference or an external voltage reference
connected to V
REF
. To minimize noise, a 0.1μF capacitor
should be connected between V
REF
and ground. I
SET
is
mirrored to each of the GBR output current sources. To
minimize noise, a 0.1μF capacitor should be connected
between the COMP pin and the analog supply voltage V
AA
.
Voltage Reference Output/Input - V
REF
An internal voltage source of +1.25V is output on the V
REF
pin. An external +1.25V reference may be applied to over-
ride the internal reference. Decoupling V
REF
to GND with
a 0.1µF ceramic capacitor is required.
CDK3405
8-bit, 180MSPS, Triple Video DACs
Power and Ground
Required power is a single +3.3V supply. To minimize power
supply induced noise, analog +3.3V should be connected
to all three supply pins with 0.1µF and 0.01µF decoupling
capacitors placed adjacent to each V
AA
pin or pin pair.
The high slew-rate of digital data makes capacitive cou-
pling to the outputs of any D/A converter a potential
problem. Since the digital signals contain high-frequency
components of the CLK signal, as well as the video out-
put signal, the resulting data feedthrough often looks
like harmonic distortion or reduced signal-to-noise perfor-
mance. All ground pins should be connected to a common
solid ground plane for best performance.
Rev 1B
Voltage Reference
Full scale current is a multiple of the current I
SET
through
an external resistor, R
SET
connected between the R
REF
pin
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www.cadeka.com
8
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