PRELIMINARY
Data Sheet
Table of Contents
Features
.................................................................. 1
Applications
............................................................ 1
General Description
................................................ 1
Block Diagram
........................................................ 1
Table of Contents
................................................... 2
Ordering Information
............................................. 3
Pin Configurations
.................................................. 4
Pin Assignments
.................................................. 5-8
Absolute Maximum Ratings
................................... 9
Reliability Information
........................................... 9
ESD Protection
........................................................ 9
Recommended Operating Conditions
.................... 9
Electrical Characteristics
...................................... 10
Electrical Characteristics – CDK8307A
................ 10
Electrical Characteristics – CDK8307B
................ 11
Electrical Characteristics – CDK8307C
................ 11
Electrical Characteristics – CDK8307C
Table 6. LVDS Output Drive Strength for
LCLK, FCLK, and Data ............................... 18
Table 7. LVDS Internal Termination
CDK8307
12/13-bit,
20/40/50/65MSPS,
Eight Channel, Ultra Low Power ADC with LVDS
Programmability ....................................... 19
Table 8. Bit Clock Internal Termination .................... 19
Table 9. Analog Input Invert................................... 19
Table 10. LVDS Test Patterns .................................. 20
Table 11. Programmable Gain................................. 20
Table 12. Gain Setting for Channels 1-8 .................. 21
Table 13. LVDS Clock Programmability and
Data Output Modes ................................. 21
Figure 6. Phase Programmability Modes for LCLK ..... 22
Figure 7. SDR Interface Modes ............................... 22
Table 14. Number of Serial Output Bits ................... 22
Table 15. Full Scale Control .................................... 23
Table 16. Register Values with Corresponding
Charge in Full-Scale Range ...................... 23
Table 17. Clock Frequency ...................................... 23
Table 18. Clock Frequency Settings ......................... 23
Table 19. Performance Control................................ 24
Table 20. Performance Control Settings ................... 24
Table 21. External Common Mode Voltage
Buffer Driving Strength ........................... 24
Theory of Operation
............................................. 25
Recommended Usage
........................................... 25
Analog Input ......................................................... 25
Figure 8. Input Configuration Diagram
................ 25
DC-Coupling.......................................................... 25
Figure 9. DC-Coupled Input ................................ 25
AC-Coupling .......................................................... 26
Figure 10. Transformer Coupled Input ................. 26
Figure 11. AC-Coupled Input .............................. 26
Figure 12. Alternative Input Network................... 26
Clock Input and Jitter Considerations ...................... 27
Mechanical Dimensions
...................................28-29
QFN-64 Package.................................................... 28
TQFP-80 Package .................................................. 29
(Continued)
........................................................... 12
Electrical Characteristics – CDK8307D
................ 12
Digital and Timing Electrical Characteristics
...... 13
LVDS Timing Diagrams
......................................... 14
Figure 1. 12-bit Output, DDR Mode......................... 14
Figure 2. 14-bit Output, DDR Mode......................... 14
Figure 3. 12-bit Output, SDR Mode ......................... 14
Figure 4. Data Timing ............................................ 14
Serial Interface
..................................................... 15
Timing Diagram .................................................... 15
Figure 5. Serial Port Interface Timing Diagram ..... 15
Table 1. Serial Port Interface Timing Definitions
... 15
Register Initialization ............................................. 15
Serial Register Map
..........................................16-17
Table 2. Summary of Functions Supported
by Serial Interface ................................16-17
Description of Serial Registers
........................17-24
Table 3. Software Reset ......................................... 17
Table 4. Power-Down Modes .................................. 17
Table 5. LVDS Drive Strength Programmability ......... 18
Rev 0.4.0
©2009 CADEKA Microcircuits LLC
www.cadeka.com
2
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
