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CDK8307CILP64B2 参数 Datasheet PDF下载

CDK8307CILP64B2图片预览
型号: CDK8307CILP64B2
PDF下载: 下载PDF文件 查看货源
内容描述: 12月13日位, 20/40/ 50 / 65MSPS ,八通道,超低功耗ADC LVDS [12/13-bit, 20/40/50/65MSPS, Eight Channel, Ultra Low Power ADC with LVDS]
分类和应用:
文件页数/大小: 29 页 / 1423 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
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PRELIMINARY
Data Sheet
Pin Assignments
(Continued)
Pin No.
51, 54, 55, 56
53
58
59
60
61
62
63
64
1, 4, 7, 8, 11, 12, 37, 42, 45, 48,
51, 59, 62
0
60
61
64
63
2
3
6
5
43
44
47
46
49
50
53
52
13, 36
14, 35
41
22
21
20
19
18
17
16
15
34
33
Pin Name
NC
VCM
CLKP
CLKN
OVDD
CSN
SDATA
SCLK
RESETN
Description
Not connected
Common mode output pin, 0.5 AVDD
Positive differential input clock
Negative differential input clock.
Digital CMOS inputs supply voltage (1.7V to 3.6V)
Chip select enable. Active low.
Serial data input
Serial clock input
Reset SPI interface
CDK8307
12/13-bit,
20/40/50/65MSPS,
Eight Channel, Ultra Low Power ADC with LVDS
QFN-64
(B2 version: AD9222 pinout option)
AVDD
AVSS
IP1
IN1
IP2
IN2
IP3
IN3
IP4
IN4
IP5
IN5
IP6
IN6
IP7
IN7
IP8
IN8
DVSS
DVDD
PD
D1P
D1N
D2P
D2N
D3P
D3N
D4P
D4N
D5P
D5N
Analog power supply, 1.8V
Analog ground (Exposed paddle, Pin 0, bottom of package)
Positive differential input signal, channel 1
Negative differential input signal, channel 1
Positive differential input signal, channel 2
Negative differential input signal, channel 2
Positive differential input signal, channel 3
Negative differential input signal, channel 3
Positive differential input signal, channel 4
Negative differential input signal, channel 4
Positive differential input signal, channel 5
Negative differential input signal, channel 5
Positive differential input signal, channel 6
Negative differential input signal, channel 6
Positive differential input signal, channel 7
Negative differential input signal, channel 7
Positive differential input signal, channel 8
Negative differential input signal, channel 8
Digital ground
Digital and I/O power supply, 1.8V
Power-down input
LVDS channel 1, positive output
LVDS channel 1, negative output
LVDS channel 2, positive output
LVDS channel 2, negative output
LVDS channel 3, positive output
LVDS channel 3, negative output
LVDS channel 4, positive output
LVDS channel 4, negative output
LVDS channel 5, positive output
LVDS channel 5, negative output
Rev 0.4.0
©2009 CADEKA Microcircuits LLC
www.cadeka.com
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