TMC22x5yA
PRODUCT SPECIFICATION
Pin Descriptions
Pin Name
Inputs
VIDEOA
9-0
86, 85, 84, 83,
82, 81, 80, 79,
78, 77
75, 74, 73, 72,
71, 70, 69, 68,
67, 66
49
TTL
Video input A.
An 8 or 10 bit data input to the input multiplexer.
For 8-bit versions (TMC2205yA) the data are left-justified (VIDEOA
9-2
).
Video input B.
An 8 or 10 bit data input to the input multiplexer.
For 8-bit versions (TMC2205yA) the data are left-justified (VIDEOB
9-2
).
Vertical sync input.
A vertical sync signal (active low) occurring at the
start of the first vertical sync pulse in a vertical field group. A falling edge
of VSYNC which is coincident with a falling edge of HSYNC indicates
field 1. This signal is active only when SPGIP
1-0
= 00.
Horizontal sync input.
A horizontal sync signal (active low) occurring
at the falling edge of the video sync. This signal is active only when
SPGIP
1-0
= 00.
Master decoder control.
00
01
10
11
BUFFER
50
TTL
Adaptive comb decoder
Simple bandsplit decoder
Reserved
Flat notched luma and simple bandsplit chroma
Pin Number
Value
Pin Function Description
VIDEOB
9-0
TTL
VSYNC
TTL
HSYNC
48
TTL
MASTER
1-0
88, 87
TTL
Control register select.
This signal switches between two sets of
registers which control the gain or hue values in the output matrix.
When BUFFER = 0, registers 17-1F are active. When BUFFER = 1,
registers 27-2F take control.
Master processing clock.
The clock signal can either be at twice the
pixel data rate in the line locked modes, or at four times the subcarrier
frequency in the subcarrier mode. The interpretation of the CLOCK
signal is set by the CKSEL register bit.
Programmable function pin.
The function specified by the SET
register is active when SET is low. The decoder returns to its previous
operation when SET goes high.
Green or Luminance digital output.
For 8-bit versions (TMC2205yA)
the data are left-justified (G/Y
9-2
).
Blue or C
B
digital output.
For 8-bit versions (TMC2205y) the data are
left-justified (B/C
B 9-2
).
Red or C
R
digital output.
For 8-bit versions (TMC2205yA) the data are
left-justified (R/C
R 9-2
).
Vertical sync output.
The DVSYNC signal occurs once per field and
lasts for 1 video line.
Horizontal sync output.
The DHSYNC signal occurs once per line and
lasts for 64 clock periods.
Data synchronization output.
LDV can be an internally or externally
generated clock signal. The internal LDV signal is produced when the
CLOCK input is at twice the pixel data rate (PXCK); and is a pixel data
rate clock phase locked to the falling edge of the HSYNC. The external
LDV can be selected under software control, and must be at the
CLOCK, or a sub multiple of the CLOCK, frequency.
CLOCK
89
TTL
SET
52
TTL
Outputs
G/Y
9-0
93, 94, 95, 96,
97, 98, 99, 100,
1, 2
6, 7, 8, 9, 10,
11, 12, 13, 14,
15
18, 19, 20, 21,
22, 23, 24, 25,
26, 27
35
34
3
TTL
B/C
B9-0
TTL
R/C
R9-0
TTL
DVSYNC
DHSYNC
LDV
TTL
TTL
TTL
6
REV. 1.0.0 2/4/03
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
