TMC22x5yA
PRODUCT SPECIFICATION
Control Register Map
The TMC22x5yA is initialized and controlled by a set of
registers which determine the operating modes.
An external controller is employed to write and read the
Control Registers through either the 8-bit parallel or 2-line
serial interface port. The parallel port, D
7-0
, is governed by
pins CS, R/W, and A
1-0
. The serial port is controlled by SDA
and SCL.
Reg
00
00
00
00
00
01
01
01
01
01
01
01
01
02
02
02
02
02
02
02
03
03
03
03
03
04
05
Bit
7
6
5-3
2
1-0
7
6
5
4
3
2
1
0
7
6
5-4
3
2
1
0
7-5
4
3-2
1
0
7-0
7-0
IPMUX
IP8B
TDEN
TBLK
IPCMSB
ABMUX
CKSEL
BLLRST
VIPEN
LOCK
BLM
KILD
DMODBY
CINT
BLFS
CCEN
CCOR
GAUBY
GAUSEL
BTH
PED
Name
Global Control
SRST
HRST
SET
DHVEN
STD
Software reset
Hardware reset
SET pin function
Output H&V sync enable
Selects video standard
reserved, set to zero
Input mux control
8 bit input format
TRS detect enable
TRS blank enable
Chroma input msb invert
AB mux control
Input clock rate select
BLL auto. reset enable
Video Input Processor
enable
Global lock mode
BLL lock mode
Color kill disable
Demod bypass
C
B
C
R
interpolation enable
Burst loop filter select
Chroma coring enable
Chroma coring threshold
Gaussian filter bypass
Gaussian filter select
Burst threshold
Pedestal
Pedestal level
Function
Reg
06
06
06
06
06
06
07
07
07
07
07
07
07
07
Bit
7-6
5
4
3-2
1
0
7
6
5
4
3
2
1
0
Name
Function
reserved, set to zero
Luma Processor Control
ANEN
ANR
ANT
ANSEL
NOTCH
LS1BY
LS1IN
LS2DLY
SPLIT
BSFBY
BSFSEL
BSFMSB
GRSDLY
Adaptive notch enable
Adaptive notch rounding
Adaptive notch threshold
Adaptive notch select
Notch enable
Line store 1 bypass
Line store 1 input
Line store 2 delay
Line store 2 data width
Bandsplit filter bypass
Bandsplit filter select
Inverts msb of bandsplit
filter
Delays input to GRS
decode by 1H
Mid-sync level
Extended DRS
09
09
0A
0A
0A
0A
0A
0A
0B
0B
0B
0B
0B
0B
0C
0C
0C
0C
7-4
3-0
7
6-5
4-3
2
1
0
7
6
5
4-2
1
0
7-6
5
4
3-0
DRSEN
DRSCK
ADAPT
YCES
YCSEL
COMB
PCKF
VSTD
OP8B
OPLMT
MSEN
OPCMSB
YBAL
BUREN
FMT422
CDEC
YUVT
Clock rate
Video standard
Output rounded to 8 bits
Output limit select
Mixed sync enable
Chroma output msb invert
Luma color correction
Output burst enable
Enables C
B
C
R
output mux
C
B
C
R
decimation enable
Enables D1 output
reserved, set to zero
DRS output enable
DRS data rate
Adaption mode
YC input error signal
control
luma/chroma comb filter
select
Comb filter architecture
Comb Processor Control
Input Processor Control
Mid-Sync Level
08
7-0
MIDS
Burst Loop Control
Output Control
Chroma Processor Control
Comb Filter Control
Burst Threshold
8
REV. 1.0.0 2/4/03
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
