TMC2242A/TMC2242B
PRODUCT SPECIFICATION
Timing Diagrams (continued)
t
ENA
t
OE
0.5V
DIS
Three-State
Outputs
2.0V
0.8V
0.5V
High Impedance
65-2242A-11
Figure 9. Threshold Levels for Three State Measurements
Applications Discussion
The TMC2242A and TMC2242B are well-suited for filtering
digitized composite NTSC or PAL video. In Figure 10, the
In Figure 11, the TMC2242B drives a fast D/A converter to
reconstruct analog composite video. The TMC3003 10-bit
TMC1175A 8-bit video A/D converter outputs, D , are
7-0
digital-to-analog converter inputs, D are connected to the
9-0
connected to the TMC2242B inputs, SI , respectively
11-4
TMC2242B outputs SO , respectively. The TMC2242B
15-6
(grounding SI ). The RND controls are set to 111 for a
3-0 2-0
RND controls are set to 110 for rounded 10-bit interpola-
2-0
9-bit rounded decimated output on SO
.
tion operation.
15-7
TTL Clock
27.000 MHz (D1)
28.636 MHz (NTSC D2)
D
SI
11
7
2 uH
2 uH
MSB
8
TMC1175A
8-bit A/D
TMC2242B
VIN
Composite
Video
SO
15
SI
300 pF
510 pF
10-4
7
75 Ohm
D
DEC=0
TCO=INT=1
6-0
75 Ohm
300 pF
9
SO
14-7
AGND
27.000 MHz (D1)
28.636 MHz (NTSC D2)
13.500 MHz (D1)
14.318 MHz (NTSC D2)
65-2242A-12
Figure 10. Decimating Oversampled Video With a Low Cost 8-bit A/D
TTL Clock
27.000 MHz (D1)
28.636 MHz (NTSC D2)
TMC3003
MSB
SO
TMC2242B
D
D
15
9
2 uH
SI
2 uH
10-bit D/A
11
I
OUT
9
SO
8-0
14-6
Composite
Video
75 Ohm
11 LSB SI
12
10-0
300 pF
510 pF
300 pF
75 Ohm
AGND
TCO=1 INT=DEC=0
13.500 MHz (D1)
14.318 MHz (NTSC D2)
27.000 MHz (D1)
28.636 MHz (NTSC D2)
65-2242A-13
Note: Data buses are unsigned binarys; TMC2242 input is two’s complement.
Figure 11. Interpolating Digital Video Signals before Reconstruction
11
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