TMC2242A/TMC2242B
PRODUCT SPECIFICATION
Table 4b. Output Data Formats and Bit Weighting for TCO = 1
Interpolation Mode
(TMC2242A and TMC2242B when INT = 0 and DEC = 1)
-2
1
2
0
2
-1
…
2
6
2
-7
2
-8
2
-9
2
-10
2
-11
2
-12
2
-13
2
-14
Decimation, Equal Rate Modes
(and TMC2242B in unity gain interpolate mode with INT = DEC = 0)
-2
0
2
-1
2
-2
…
2
-7
2
-8
2
-9
2
-10
2
-11
2
-12
2
-13
2
-14
2
-15
Rounded LSBs as a function of RND
2-0
RND
2-0
SO
15
SO
15
SO
15
SO
15
SO
15
SO
15
SO
15
SO
15
SO
14
SO
14
SO
14
SO
14
SO
14
SO
14
SO
14
SO
14
SO
13
SO
13
SO
13
SO
13
SO
13
SO
13
SO
13
SO
13
…
…
…
…
…
…
…
…
SO
8
SO
8
SO
8
SO
8
SO
8
SO
8
SO
8
SO
8
SO
7
SO
7
SO
7
SO
7
SO
7
SO
7
SO
7
SO
7r
SO
6
SO
6
SO
6
SO
6
SO
6
SO
6
SO
6r
0
SO
5
SO
5
SO
5
SO
5
SO
5
SO
5r
0
0
SO
4
SO
4
SO
4
SO
4
SO
4r
0
0
0
SO
3
SO
3
SO
3
SO
3r
0
0
0
0
SO
2
SO
2
SO
2r
0
0
0
0
0
SO
1
SO
1r
0
0
0
0
0
0
SO
0r
0
0
0
0
0
0
0
000
001
010
011
100
101
110
111
Notes:
1. A leading minus sign denotes the two’s complement sign bit.
2. When TCO=0, the most significant bit of the output is positive instead of negative.
3. In all operating modes except
INT
= 0 and
DEC
= 1, the gain is approximately unity. When
INT
= 0 and
DEC
= 1, the output
gain is -6 dB.
4. The "r" indicates that the trailing significant output bit has been rounded to the nearest 1/2 LSB. (Internally, the chip adds 1 to
the next lower bit, to allow the user to obtain a properly rounded output)
Table 5. TMC2242A Steady-State Output Values and Limiter Triggers (L) versus Input Data
INT
= 1 or
DEC
= 0
Input
7FF
400
001
000
FFF
C00
801
TCO = 0
0000 (L)
3FE7
7FEF
7FFF
800F
C017
FFFF (L)
TCO = 1
7FFF (L)
4018
0010
0000
FFF0
BFE8
8000 (L)
INT
= 0 and
DEC
= 1
TCO = 0
3FF7 / 3FE7
5FF7 / 5FEF
7FF7
7FFF
8007
A007 / A00F
C007 / C017
TCO = 1
4008 / 4018
2008 / 2010
0008
0000
FFF8
DFF8 / DFF0
BFF8 / BFE8
Interpretation
+ full-scale
+1/2 scale
+1 LSB
Zero
-1 LSB
-1/2 scale
- full-scale
7
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