PRODUCT SPECIFICATION
TMC2246A
Pin Descriptions
(continued)
Pin Number
Pin Name
Controls
FSEL
B2
2
Format Select.
Coefficients input during the current clock are
assumed to be in fractional two's complement format. Rounding to
16 bits is performed as determined by the accumulator control,
ACC, and the upper 16 bits of the accumulator are output when
the registered Format Select input (FSEL) is LOW. When FSEL is
HIGH, two's complement integer format is assumed, and the
lower 16 bits of the accumulator are presented at the output. No
rounding is performed when operating in integer mode. See the
Functional Block Diagram and the Applications Discussion.
Enable Select.
The registered Enable Select determines whether
the data or the coefficient input registers may be held on the next
rising edge of clock, in conjunction with the individual input
enables ENB1–ENB4. See Table 1.
Input Enables.
When ENBi (i=1, 2, 3, or 4) is LOW, registers Ci
and Di are both strobed by the next rising edge of CLK. When
ENBi is HIGH and ENSEL is LOW, Di is strobed, but Ci is held.
When ENBi and ENSEL are both HIGH, Di is held and Ci is
strobed. See Table 1. Thus, either or both input registers to each
multiplier are updated on each clock cycle.
Accumulate.
When the registered ACCumulator control is LOW,
no internal accumulation will be performed on the data input
during the current clock, effectively clearing the prior accumulated
sum. If operating in fractional two's complement format (FSEL =
LOW), one-half LSB rounding to 16 bits is performed on the result.
This allows the user to perform summations without propagating
roundoff errors.
When ACC is HIGH, the internal accumulator adds the emerging
products to the sum of previous products, without performing
additional rounding.
OCEN
D3
4
Output Register Enable.
The output of the accumulator is
latched into the output register on the next clock when the Output
Register Clock Enable is LOW. When OCEN is HIGH the contents
of the output register remain unchanged; however, accumulation
will continue internally if ACC remains HIGH.
Output Enable.
Data currently in the output registers is available
at the output bus S
15-0
when the asynchronous Output Enable is
LOW. When OEN is HIGH, the outputs are in the high-impedance
state.
Not Connected. (Optional)
CPGA/PPGA/
MPGA
MQFP
Pin Function Description
ENSEL
A1
120
ENB1–
ENB4
C4, A2, A3, B3
118, 117, 116,
119
ACC
B1
3
OEN
C2
5
No Connect
NC
D4 (Index Pin)
Note:
1. X denotes a "Don't Care" condition.
2. Any register not explicitly held is updated on the next rising edge of CLK.
6
REV. 1.0.3 9/11/00
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
