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CAT1023WI-28-T3 参数 Datasheet PDF下载

CAT1023WI-28-T3图片预览
型号: CAT1023WI-28-T3
PDF下载: 下载PDF文件 查看货源
内容描述: 监控电路,带有I2C串行2K位CMOS EEPROM ,手动复位及看门狗定时器 [Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer]
分类和应用: 监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 21 页 / 203 K
品牌: CATALYST [ CATALYST SEMICONDUCTOR ]
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CAT1021, CAT1022, CAT1023
RESET CIRCUIT AC CHARACTERISTICS
Symbol
t
PURST
t
RDP
t
GLITCH
MR Glitch
t
MRW
t
MRD
t
WD
Parameter
Power-Up Reset Timeout
V
TH
to RESET output Delay
V
CC
Glitch Reject Pulse Width
Manual Reset Glitch Immunity
MR Pulse Width
MR Input to RESET Output Delay
Watchdog Timeout
Test Conditions
Note 2
Note 3
Note 4, 5
Note 1
Note 1
Note 1
Note 1
1.0
1.6
5
1
2.1
Min
130
Typ
200
Max
270
5
30
100
Units
ms
µs
ns
ns
µs
µs
sec
POWER-UP TIMING
(5), (6)
Symbol
t
PUR
t
PUW
Parameter
Power-Up to Read Operation
Power-Up to Write Operation
Test Conditions
Min
Typ
Max
270
270
Units
ms
ms
AC TEST CONDITIONS
Parameter
Input Pulse Voltages
Input Rise and Fall times
Input Reference Voltages
Output Reference Voltages
Output Load
RELIABILITY CHARACTERISTICS
Symbol
N
END
(5)
Test Conditions
0.2V
CC
to 0.8V
CC
10ns
0.3V
CC
, 0.7V
CC
0.5V
CC
Current Source: I
OL
= 3mA; C
L
= 100pF
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2000
100
Max
Units
Cycles/Byte
Years
Volts
mA
T
DR(5)
V
ZAP(5)
I
LTH(5)(7)
Notes:
(1) Test Conditions according to “AC Test Conditions” table.
(2) Power-up, Input Reference Voltage V
CC
= V
TH
, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
(3) Power-Down, Input Reference Voltage V
CC
= V
TH
, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
(4) V
CC
Glitch Reference Voltage = V
THmin
; Based on characterization data
(5) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(6) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified memory operation can be initiated.
(7) Latch-up protection is provided for stresses up to 100mA on input and output pins from -1V to V
CC
+ 1V.
Doc. No. MD-3009 Rev. M
6
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice