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CAT1161WI-28-GT3 参数 Datasheet PDF下载

CAT1161WI-28-GT3图片预览
型号: CAT1161WI-28-GT3
PDF下载: 下载PDF文件 查看货源
内容描述: 监控电路,带有I2C串行EEPROM CMOS ,精密复位控制器和看门狗定时器( 16K ) [Supervisory Circuits with I2C Serial CMOS EEPROM, Precision Reset Controller and Watchdog Timer (16K)]
分类和应用: 电源电路电源管理电路光电二极管监控输入元件控制器可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 14 页 / 204 K
品牌: CATALYST [ CATALYST SEMICONDUCTOR ]
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CAT1161, CAT1162
D.C. OPERATING CHARACTERISTICS
V
CC
= 2.7V to 6V, unless otherwise specified.
Symbol
I
CC
I
SB
I
LI
I
LO
V
IL
V
IH
V
OL1
Parameter
Power Supply Current
Standby Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (SDA)
I
OL
= 3 mA, V
CC
= 3.0V
Test Conditions
f
SCL
= 100 KHz
V
CC
= 3.3V
V
CC
= 5
V
IN
= GND or V
CC
V
IN
= GND or V
CC
-1
V
CC
x 0.7
Min
Typ
Max
3
40
50
2
10
V
CC
x 0.3
V
CC
+ 0.5
0.4
Units
mA
µA
µA
µA
µA
V
V
V
CAPACITANCE
T
A
= 25ºC, f = 1.0MHz, V
CC
= 5V
Symbol
C
I/O(1)
C
IN
(1)
Test
Input/Output Capacitance (SDA)
Input Capacitance (SCL)
Conditions
V
I/O
= 0V
V
IN
= 0V
Max
8
6
Units
pF
pF
A.C. CHARACTERISTICS
V
CC
= 2.7V to 6.0V unless otherwise specified. Output Load is 1 TTL Gate and 100pF.
Symbol
F
SCL
T
I(1)
t
AA
t
BUF(1)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R(1)
t
F(1)
t
SU:STO
t
DH
Parameter
Clock Frequency
Noise Suppresion Time Constant at SCL, SDA Inputs
SLC Low to SDA Data Out and ACK Out
Time the Bus Must be Free Before a New Transmission
Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time (for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
4
100
4.7
4
4.7
4
4.7
0
50
1
300
0.6
100
Min
Max
100
200
3.5
1.2
0.6
1.2
0.6
0.6
0
50
0.3
300
Min
Max
400
200
1
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
POWER-UP TIMING
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max
1
1
Units
ms
ms
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specific operation can be initiated.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. MD-3002 Rev. G