CAT1161, CAT1162
WRITE CYCLE LIMITS
Symbol
t
WR
Parameter
Write Cycle Time
Min
Typ
Max
10
Units
ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave address.
RESET CIRCUIT CHARACTERISTICS
Symbol
t
GLITCH
V
RT
V
OLRS
V
OHRS
Parameter
Glitch Reject Pulse Width
Reset Threshold Hystersis
Reset Output Low Voltage (I
OLRS
=1mA)
Reset Output High Voltage
Reset Threshold (V
CC
=5V)
(CAT1161/2-45)
Reset Threshold (V
CC
=5V)
(CAT1161/2-42)
V
TH
Reset Threshold (V
CC
=3.3V)
(CAT1161/2-30)
Reset Threshold (V
CC
=3.3V)
(CAT1161/2-28)
Reset Threshold (V
CC
=3V)
(CAT1161/2-25)
t
PURST
t
WP
t
RPD
V
RVALID
Power-Up Reset Timeout
Watchdog Period
V
TH
to RESET Output Delay
RESET Output Valid
1
V
CC
- 0.75
4.50
4.25
3.00
2.85
2.55
130
1.6
5
4.75
4.50
3.15
3.00
2.70
270
ms
sec
µs
V
V
15
0.4
Min
Typ
Max
100
Units
ns
mV
V
V
Doc. No. 3002 Rev. F
4
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CATALYST [ CATALYST SEMICONDUCTOR ]
