CAT24C128
Figure 5. Byte Write Sequence
BUS ACTIVITY:
MASTER
S
T
A
R
T
SLAVE
ADDRESS
ADDRESS
BYTE
a13–a8
ADDRESS
BYTE
a7–a0
DATA
BYTE
S
T
O
P
P
S
SLAVE
A
C
K
**
A
C
K
A
C
K
A
C
K
*
= Don't Care Bit
Figure 6. Write Cycle Timing
SCL
SDA
8th Bit
Byte n
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 7. Page Write Sequence
BUS ACTIVITY:
MASTER
S
T
A
R
T
S
SLAVE
A
C
K
ADDRESS
BYTE
a13–a8
ADDRESS
BYTE
a7–a0
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+P
S
T
O
P
P
SLAVE
ADDRESS
**
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
*
= Don't Care Bit
P
≤
63
Figure 8. WP Timing
ADDRESS
BYTE
1
SCL
8
9
1
DATA
BYTE
8
SDA
a7
a0
tSU:WP
d7
d0
WP
tHD:WP
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc No. MD-1103, Rev. J