CAT24C128
READ OPERATIONS
Immediate Read
Upon receiving a Slave address with the R/W bit set to
‘1’, the CAT24C128 will interpret this as a request for
data residing at the current byte address in memory.
The CAT24C128 will acknowledge the Slave address,
will immediately shift out the data residing at the current
address, and will then wait for the Master to respond.
If the Master does not acknowledge the data (NoACK)
and then follows up with a STOP condition (Figure 9),
the CAT24C128 returns to Standby mode.
Selective Read
To read data residing at a specific location, the internal
address counter must first be initialized as described
under Byte Write. If rather than following up the two
address bytes with data, the Master instead follows up
with an Immediate Read sequence, then the CAT24C128
will use the 14 active addres bits to initialize the inter-
nal address counter and will shift out data residing at
the corresponding location. If the Master does not ac-
knowledge the data (NoACK) and then follows up with
a STOP condition (Figure 10), the CAT24C128 returns
to Standby mode.
Sequential Read
If during a Read session the Master acknowledges the
1
st
data byte, then the CAT24C128 will continue trans-
mitting data residing at subsequent locations until the
Master responds with a NoACK, followed by a STOP
(Figure 11). In contrast to Page Write, during Sequential
Read the address count will automatically increment to
and then wrap-around at end of memory (rather than
end of page).
Doc. No. MD-1103, Rev. J
8
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CATALYST [ CATALYST SEMICONDUCTOR ]
