CAT25010, CAT25020, CAT25040
Byte Write
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, a 8-bit
address and data as shown in Figure 4. For the
CAT25040, bit 3 of the write instruction opcode
contains A8 address bit. Internal programming will
¯¯
start after the low to high CS transition. During an
internal write cycle, all commands, except for RDSR
(Read Status Register) will be ignored. The ¯¯¯¯ bit
RDY
will indicate if the internal write cycle is in progress
¯¯¯¯
(RDY high), or the the device is ready to accept
¯¯¯¯
commands (RDY low).
Page Write
After sending the first data byte to the
CAT25010/20/40, the host may continue sending
data, up to a total of 16 bytes, according to timing
shown in Figure 5. After each data byte, the lower
order address bits are automatically incremented,
while the higher order address bits (page address)
remain unchanged. If during this process the end of
page is exceeded, then loading will “roll over” to the
first byte in the page, thus possibly overwriting
previoualy loaded data. Following completion of the
write cycle, the CAT25010/20/40 is automatically
returned to the write disable state.
Figure 4. Byte WRITE Timing
CS
0
SCK
OPCODE
1
2
3
4
5
6
7
8
13
14
15
16
17
18
19
20
21
22
23
BYTE ADDRESS
0
1
0
A7
DATA IN
SI
0
0
0
0
X*
A0 D7 D6 D5 D4 D3 D2 D1 D0
SO
HIGH IMPEDANCE
Notes:
Dashed Line = mode (1, 1) - - - - - -
* X = 0 for CAT25010, CAT25020. x = A8 for CAT25040
Figure 5. Page WRITE Timing
CS
0
SCK
OPCODE
1
2
3
4
5
6
7
8
13
14
15 16-23 24-31
16+(N-1)x8-1..16+(N-1)x8 16+Nx8-1
BYTE ADDRESS
0
1
0
A
7
A
0
Data
Byte 1
DATA IN
Data
Byte 2
Data
Byte 3
Data Byte N
0
7..1
SI
0
0
0
0
X*
SO
HIGH IMPEDANCE
Notes:
Dashed Line = mode (1, 1) - - - - - -
* X = 0 for CAT25010, CAT25020. x = A8 for CAT25040
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc. No. MD-1006 Rev. T
CATALYST [ CATALYST SEMICONDUCTOR ]
