CAT25080, CAT25160
Hold Operation
The ¯¯¯¯¯ input can be used to pause communication
HOLD
¯¯¯¯¯
between host and CAT25080/160. To pause, HOLD
must be taken low while SCK is low (Figure 10). During
¯¯
the hold condition the device must remain selected (CS
low). During the pause, the data output pin (SO) is tri-
stated (high impedance) and SI transitions are ignored.
¯¯¯¯¯
To resume communication, HOLD must be taken high
while SCK is low.
The CAT25080/160 device powers up in a write disable
state and in a low power standby mode. A WREN
instruction must be issued prior any writes to the device.
After power up, the CS pin must be brought low to enter
a ready state and receive an instruction. After a
successful byte/page write or status register write, the
device goes into a write disable mode. The CS input
must be set high after the proper number of clock cycles
to start the internal write cycle. Access to the memory
array during an internal write cycle is ignored and
programming is continued. Any invalid op-code will be
ignored and the serial output pin (SO) will remain in the
high impedance state.
DESIGN CONSIDERATIONS
The CAT25080/160 devices incorporate Power-On
Reset (POR) circuitry which protects the internal logic
against powering up in the wrong state. The device will
power up into Standby mode after V
CC
exceeds the
POR trigger level and will power down into Reset mode
when V
CC
drops below the POR trigger level. This bi-
directional POR behavior protects the device against
‘brown-out’ failure following a temporary loss of power.
¯¯¯¯¯
Figure 10. HOLD Timing
CS
tCD
SCK
tHD
HOLD
tHZ
SO
tHD
tCD
HIGH IMPEDANCE
tLZ
Note:
Dashed Line = mode (1, 1) - - - - - -
Doc. No. 1122 Rev. A
10
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CATALYST [ CATALYST SEMICONDUCTOR ]
