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CAT25160HU2I-GT3 参数 Datasheet PDF下载

CAT25160HU2I-GT3图片预览
型号: CAT25160HU2I-GT3
PDF下载: 下载PDF文件 查看货源
内容描述: 8 KB和16 KB的SPI串行EEPROM CMOS [8-Kb and 16-Kb SPI Serial CMOS EEPROM]
分类和应用: 内存集成电路可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 17 页 / 254 K
品牌: CATALYST [ CATALYST SEMICONDUCTOR ]
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CAT25080, CAT25160
Byte Write
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, a 16-bit
address and data as shown in Figure 4. Only 10
significant address bits are used by the CAT25080 and
11 by the CAT25160. The rest are don’t care bits, as
shown in Table 5. Internal programming will start after
¯¯
the low to high CS transition. During an internal write
cycle, all commands, except for RDSR (Read Status
Register) will be ignored. The ¯¯¯¯ bit will indicate if the
RDY
¯¯¯¯
internal write cycle is in progress (RDY high), or the the
¯¯¯¯
device is ready to accept commands (RDY low).
Page Write
After sending the first data byte to the CAT25080/160,
the host may continue sending data, up to a total of 32
bytes, according to timing shown in Figure 5. After each
data byte, the lower order address bits are automatically
incremented, while the higher order address bits (page
address) remain unchanged. If during this process the
end of page is exceeded, then loading will “roll over” to
the first byte in the page, thus possibly overwriting
previoualy loaded data. Following completion of the
write cycle, the CAT25080/160 is automatically returned
to the write disable state.
Table 5. Byte Address
Device
CAT25080
CAT25160
Address Significant Bits
A9 - A0
A10 - A0
Address Don't Care Bits
A15 - A10
A15 - A11
# Address Clock Pulse
16
16
Figure 4. Byte WRITE Timing
CS
0
SCK
OPCODE
1
2
3
4
5
6
7
8
21
22
23
24
25
26
27
28
29
30
31
BYTE ADDRESS*
1
0
AN
DATA IN
SI
0
0
0
0
0
0
A0 D7 D6 D5 D4 D3 D2 D1 D0
SO
HIGH IMPEDANCE
* Please check the Byte Address Table (Table 5)
Note:
Dashed Line = mode (1, 1) - - - - - -
Figure 5. Page WRITE Timing
CS
0
SCK
OPCODE
1
2
3
4
5
6
7
8
21
22
23 24-31 32-39
24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
BYTE ADDRESS*
0
1
0
A
N
A
0
Data
Byte 1
DATA IN
Data
Byte 2
Data
Byte 3
Data Byte N
0
7..1
SI
0
0
0
0
0
SO
*Please check the Byte Address Table. (Table 5)
HIGH IMPEDANCE
Note:
Dashed Line = mode (1, 1) - - - - - -
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc. No. 1122 Rev. A