CAT28C16A
Byte Write
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 10 ms.
Figure 5. Byte Write Cycle [CE Controlled]
ADDRESS
tAS
tAH
tCW
CE
DATA Polling
DATA polling is provided to indicate the completion of a
byte write cycle. Once a byte write cycle is initiated,
attempting to read the last byte written will output the
complement of that data on I/O
7
(I/O
0
–I/O
6
are indeter-
minate) until the programming cycle is complete. Upon
completion of the self-timed byte write cycle, all I/O’s will
output true data during a read cycle.
tWC
tDL
tOEH
OE
tCS
WE
HIGH-Z
DATA OUT
tOES
tCH
DATA IN
DATA VALID
tDS
tDH
5089 FHD F07
Figure 6. DATA Polling
ADDRESS
CE
WE
tOEH
OE
tWC
I/O7
DIN = X
DOUT = X
DOUT = X
tOE
tOES
28C16A F08
Doc. No. 25033-00 2/98
7
CATALYST [ CATALYST SEMICONDUCTOR ]
