CAT34WC02
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
the byte address that is to be written into the address
pointer of the CAT34WC02. After receiving another
acknowledge from the Slave, the Master device trans-
mits the data byte to be written into the addressed
memory location. The CAT34WC02 acknowledges once
more and the Master generates the STOP condition, at
which time the device begins its internal programming to
nonvolatile memory. While this internal cycle is in
progress, the device will not respond to any request from
the Master device.
Page Write
The CAT34WC02 writes up to 16 bytes of data in a single
write cycle, using the Page Write operation. The Page
Write operation is initiated in the same manner as the
Byte Write operation, however instead of terminating
after the initial word is transmitted, the Master is allowed
to send up to 15 additional bytes. After each byte has
been transmitted the CAT34WC02 will respond with an
acknowledge, and internally increment the low order
address bits by one. The high order bits remain un-
changed.
If the Master transmits more than 16 bytes prior to
sending the STOP condition, the address counter ‘wraps
around’, and previously transmitted data will be overwrit-
ten.
Once all 16 bytes are received and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point all received data is written to
the CAT34WC02 in a single write cycle.
Acknowledge Polling
The disabling of the inputs can be used to take advan-
tage of the typical write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation, the CAT34WC02 initiates the internal write
cycle. ACK polling can be initiated immediately. This
involves issuing the start condition followed by the slave
address for a write operation. If the CAT34WC02 is still
busy with the write operation, no ACK will be returned.
If the CAT34WC02 has completed the write operation,
an ACK will be returned and the host can then proceed
with the next read or write operation.
WRITE PROTECTION
The CAT34WC02 is designed with a hardware protect
pin that enables the user to protect the entire memory.
The CAT34WC02 also has a software write protection
feature. By programming the software write protection
register, the first 128 bytes are write protected. The
software and hardware protection features of the
CAT34WC02 are designed into the part to provide
added flexibility to the design engineers.
Hardware
The write protection feature of CAT34WC02 allows the
user to protect against inadvertent programming of the
memory array. If the WP pin is tied to Vcc, the entire
Figure 6. Byte Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
S
SLAVE
ADDRESS
BYTE
ADDRESS
DATA
S
T
O
P
P
A
C
K
A
C
K
A
C
K
5020 FHD F08
Figure 7. Page Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
S
A
C
K
SLAVE
ADDRESS
*
A
C
K
A
C
K
A
C
K
A
C
K
5020 FHD F09
BYTE
ADDRESS (n)
DATA n
DATA n+1
DATA n+P
S
T
O
P
P
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
Doc. No. 1003, Rev. A
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CATALYST [ CATALYST SEMICONDUCTOR ]
